DS90C387RVJD NSC [National Semiconductor], DS90C387RVJD Datasheet
DS90C387RVJD
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DS90C387RVJD Summary of contents
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DS90C387R 85MHz Dual 12-Bit Double Pumped Input LDI Transmitter - VGA/UXGA General Description The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution designed to be ...
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Mode Configuration / PerformanceTable Mode Mode (GUI Out/Cable) Input Clock Rate (MHz) Input Data Rate (Mbps) LVDS data Pairs Out Ouput Clock Rate (MHz) Data Rate Out (Mbps) per LVDS channel Throughput Data Rate Out Generalized Block Diagrams www.national.com one ...
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Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS/LVTTL Output Voltage −0. LVDS Driver Output Voltage −0. LVDS ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified.(Note 2) Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case ICCTG Transmitter Supply Current 16 Grayscale Case ICCTZ Transmitter Supply Current Power Down Note 1: “Absolute ...
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Recommended Transmitter Input Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Device driving the transmitter inputs should comply to this table of recommendations. Symbol TCIT TxCLK IN Transition Time (Figure 5) TCIP TxCLK IN Period (Figure 6) ...
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Transmitter Switching Characteristics Note 5: The limits are based on bench characterization of the device’s jitter response over the power supply voltage range. Output clock jitter is measured with a ± cycle-to-cycle jitter of 2ns applied to the input clock ...
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AC Timing Diagrams (Continued) FIGURE 2. “16 Grayscale” Test Pattern (Note 11) Note 10: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 11: The 16 grayscale test pattern tests device ...
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AC Timing Diagrams FIGURE 4. DS90C387R LVDS Output Load and Transition Times FIGURE 6. DS90C387R TxCLK IN Period, and High/Low Time (Falling Edge Strobe) FIGURE 7. DS90C387R Setup/Hold (Falling Edge Strobe First) www.national.com (Continued) FIGURE 3. “Worst Case” Test Pattern ...
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AC Timing Diagrams (Continued) FIGURE 8. DS90C387R Phase Lock Loop Set Time FIGURE 10. DS90C387R Input to Output Latency(Note 9) FIGURE 9. DS90C387R Power Down Delay 9 10128819 10128821 10128837 www.national.com ...
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AC Timing Diagrams C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source ...
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DS90C387R Pin Description—LDI Transmitter Pin Name I/O No. D0-D23 HSYNC I 1 VSYNC I 1 AnP O 8 AnM O 8 CLKINP I 1 CLKINM I 1 R_FB I 1 R_FDE I 1 CLK1P O ...
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DS90C387R Pin Description—LDI Transmitter Pin Name I/O PLLV I CC PLLGND I LVDSV I CC LVDSGND I CLK2P/NC O CLK2M/ REF I2CSEL I DDREN/I2Cclk I DSEL/I2Cdat I MSEN O TST1 TST2 ...
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DS90C387R Pin Description—LDI Transmitter TABLE 1. Control Settings for mode selection (Continued) Mode CLKIN,single-ended/ differentail Description (Continued) 12bit Two 12-bit DSEL DSEL 12-bit in, 24-bit pixel out, Two 12-bit in, two 24-bit non-DC Balanced or pixels out, non-DC DC-Balanced Balanced ...
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DS90C387R Pin Description—LDI Transmitter TABLE 2. Relationship between R_FB, DE, HSYNC and VSYNC pins R_FB Primary Edge VCC Falling GND Rising Two-Wire Serial Communication Interface Description The DS90C387R operates as a slave on the Serial Bus, so the SCL line ...
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Two-Wire Serial Communication Interface Description TABLE 4. Register Field Definitions(’ * " = features not implemented on DS90C387R) Field Access VND_IDL RO Vendor ID low byte, value is 05h. VND_IDH RO Vendor ID high byte, value is 13h. DEV_IDL RO ...
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Two-Wire Serial Communication Interface Description TABLE 4. Register Field Definitions(’ * " = features not implemented on DS90C387R) (Continued) Field Access *VDJK [7:0] RW *DK [3:1] RW *DKEN RW Communicating with the DS90C387R through Registers There are 31 data registers ...
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Two-Wire Serial Communication Interface for Slave (Continued) The master must generate a “ Start ”, by sending the 7-bit slave address plus a 0 and wait for acknowledge from DS90C387R. When DS90C387R acknowledges (the 1st LVDS Interface ...
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LVDS Interface (Continued) TABLE 7. Two 12-bit (two data per clock) data mapping (DUAL=Vcc, BAL=Vcc/GND, A0-A7 are used). VGA - TFT Data Transmitter input pin names Signals Color Bits 24-bit LSB MSB R7 ...
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LVDS Interface (Continued) TABLE 7. Two 12-bit (two data per clock) data mapping (DUAL=Vcc, BAL=Vcc/GND, A0-A7 are used). (Continued) VGA - TFT Data Transmitter input pin names Signals Color Bits MSB B7 Note 16: The lower half ...
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LVDS Interface (Continued) TABLE 8. 12-bit (two data per clock) input application data mapping with GMCH. P0L Pin Name Low D11 G0[3] D10 G0[2] D9 G0[1] D8 G0[0] D7 B0[7] D6 B0[6] D5 B0[5] D4 B0[4] D3 B0[3] D2 B0[2] ...
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LVDS Interface (Continued) FIGURE 17. TTL Data Inputs Mapped to LVDS Outputs Non-DC Balanced Mode (Backward Compatible, BAL=Low for Port1 for Port2) 21 10128826 www.national.com ...
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LVDS Interface (Continued) FIGURE 18. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs DC Balanced Mode (Data Enabled, BAL=High for Port1 for Port2) www.national.com 22 10128804 ...
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LVDS Interface (Continued) FIGURE 19. Control Signals Transmitted During Blanking in DC-Balance mode TABLE 9. Control Signals Transmitted During Blanking in DC-Balance mode Control Signal Signal Level DE HIGH LOW HSYNC HIGH LOW VSYNC HIGH LOW Note 22: The control ...
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Applications Information How to configure the DS90C387R to work with DS90CF384/DS90CF384A/DS90CF386 or DS90CF388 for most common application configure for single pixel application using the DS90C387R to interface with GMCH host, please see table below for reference pin connection ...
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Applications Information integrated LVDS transmitter without DC balance data trans- mission. In this case, the receivers “BAL” pin must be tied low (DC balance disabled). Features Description: 1. Pre-emphasis: adds extra current during LVDS logic transition to reduce the cable ...
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Applications Information feature supports backward compatibility with the previous generation of devices - the second clock allows the transmit- ter to interface to panels using a ’dual pixel’ configuration of two 24-bit or 18-bit ’notebook’ receivers. Pre-emphasis feature is available ...
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Pin Diagram Transmitter-DS90C387R 27 10128806 www.national.com ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) Dimensions show in millimeters Order Number DS90C387RVJD NS Package Number VJD100A 2. A critical component is any component of a life ...