DS2482-100_12 MAXIM [Maxim Integrated Products], DS2482-100_12 Datasheet - Page 10

• Manufacturer Part Number: DS2482-100_12
• Description: Single-Channel 1-Wire Master
• Manufacturer: MAXIM [Maxim Integrated Products]

Single-Channel 1-Wire Master
10
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
Command Code
Command Parameter
Description
Typical Use
Restriction
Error Response
Command Duration
1-Wire Activity
Read Pointer Position
Status Bits Affected
Configuration Bits Affected
______________________________________________________________________________________
D2h
Configuration Byte
Writes a new configuration byte. The new settings take effect immediately. Note: When writing to
the Configuration Register, the new data is accepted only if the upper nibble (bits 7 to 4) is the
one’s complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
Defining the features for subsequent 1-Wire communication.
1-Wire activity must have ended before the DS2482-100 can process this command.
Command code and parameter are not acknowledged if 1WB = 1 at the time the command code
is received and the command is ignored.
None. The Configuration Register is updated on the rising SCL edge of the configuration-byte
acknowledge bit.
None
Configuration Register (to verify write).
RST set to 0.
1WS, SPU, APU updated.
B4h
None
Generates a 1-Wire reset/presence-detect cycle (Figure 4) at the 1-Wire line. The state of the
1-Wire line is sampled at t
Status Register, bits PPD and SD.
To initiate or end any 1-Wire communication sequence.
1-Wire activity must have ended before the DS2482-100 can process this command. Strong
pullup (see the SPU bit) should not be used in conjunction with the 1-Wire Reset command. If SPU
is enabled, the PPD bit may not be valid and may cause a violation of the device’s absolute
maximum rating.
Command code is not acknowledged if 1WB = 1 at the time the command code is received and
the command is ignored.
t
acknowledge bit.
Begins maximum 262.5ns after the falling SCL edge of the command code acknowledge bit.
Status Register (for busy polling).
1WB (set to 1 for t
1WS, APU, SPU apply.
RSTL
+ t
RSTH
+ maximum 262.5ns, counted from the falling SCL edge of the command code
RSTL
+ t
RSTH
SI
and t
), PPD is updated at t
MSP
and the result is reported to the host processor through the
RSTL
+ t
MSP
, SD is updated at t
Write Configuration
1-Wire Reset
RSTL
+ t
SI
.