DS2465 MAXIM [Maxim Integrated Products], DS2465 Datasheet - Page 15

• Manufacturer Part Number: DS2465
• Description: SHA-256 Coprocessor with 1-Wire Master Function
• Manufacturer: MAXIM [Maxim Integrated Products]

SHA-256 Coprocessor with 1-Wire Master Function
1-Wire Master Reset
Command Code
Parameter Byte
Usage
Other Notes
Command Restrictions
Error Conditions (Error Response)
MAC Notes
I
Command Duration
1-Wire Activity
Read Pointer Position
Master Status Bits Affected
Master Configurations Affected
1-Wire Port Configurations Affected
1-Wire Reset Pulse
Command Code
Parameter Byte
Usage
Other Notes
Command Restrictions
Error Conditions (Error Response)
MAC Notes
I
Command Duration
1-Wire Activity
Read Pointer Position
Master Status Bits Affected
Master Configurations Affected
1-Wire Port Configurations Affected
2
2
C Busy Duration
C Busy Duration
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F0h
N/A
Device initialization after power-up; re-initialization (reset) as desired.
Performs a global reset of device state machine logic. Terminates any ongoing 1-Wire
communication.
The command must be followed by a 1-Wire Reset Pulse command.
None
N/A
None
Maximum 1.635µs. Counted from rising SCL edge of the command code acknowledge
bit.
Ends maximum 1.09µs after the rising SCL edge of the command code acknowledge
bit.
(N/A)
RST set to 1; 1WB, PPD, SD, SBR, TSB, DIR set to 0.
1WS, APU, PDN, SPU set to 0.
t
B4h
N/A
To initiate or end any 1-Wire communication sequence. To finish a 1-Wire Master
Reset command.
Generates a 1-Wire reset/presence-detect cycle (Figure 5) at the 1-Wire line. The
state of the 1-Wire line is sampled at t
processor through the 1-Wire Master Status Register, bits PPD and SD.
1-Wire activity must have ended before the DS2465 can process this command.
Command code is not acknowledged if 1WB = 1 at the time the command code is
received and the command is ignored.
N/A
None
2 O t
code acknowledge bit.
Begins maximum 1.09µs after the rising SCL edge of the command code
acknowledge bit.
1-Wire Master Status register (for busy polling).
1WB (set to 1 for 2 O t
+ t
1WS and APU apply.
t
RSTL
RSTL
SI
RSTL
.
, t
, t
MSP
MSP
+ maximum 1.09µs, counted from the rising SCL edge of the command
, t
, and R
W0L
, t
WPU
W1L
RSTL
, t
current values apply.
REC0
), PPD is updated at t
, and R
WPU
SI
and t
are reset to their default values.
MSP
RSTL
and the result is reported to the host
+ t
MSP
, SD is updated at t
DS2465
RSTL