ch7307c Chrontel, ch7307c Datasheet - Page 6

• Manufacturer Part Number: ch7307c
• Description: Ch7307 Dvi Transmitter Sdvo
• Manufacturer: Chrontel

CHRONTEL
2.0 F
2.1
2.1.1 Overview
One pair of differential clock signal and three differential pairs of data signals (R/G/B) form one channel data. The
input data are 10-bit serialized data. Input data run at 1Gbits/s~2Gbits/s, being a 10x multiple of the clock rate
(SDVO_CLK+/-). The CH7307C de-serializes the input into 10-bit parallel data with synchronization and
alignment. Then the 10-bit characters are mapped into 8-bit color data or control data (Hsync, Vsync, DE).
2.1.2 Interface Voltage Levels
All differential SDVO pairs are AC coupled differential signals. Therefore, there is not a specified DC signal level
for the signals to operate at. The differential p-p input voltage has a min of 175mV, and a max of 1.2V. The
differential p-p output voltage has a min of 0.8V, with a max of 1.2V.
2.1.3 Input Clock and Data Timing
A data character is transmitted least significant bit first. The beginning of a character is noted by the falling edge of
the SDVO_CLK+ edge. The skew among input lanes is required to be no larger than 2ns.
The clock is from 100MHz~200MHz. The pixel rate can be 25MP/s~165MP/s. The pixel rate and the clock rate are
not always equal. The clock rate can be a multiple of the pixel rate (1x, 2x, or 4x depending on the pixel rate) so that
the clock rate will stay in the 100MHz~200MHz range. In the condition that the clock is running at a multiple of the
pixel rate, there isn’t enough pixel data to fill the data channels. Dummy fill characters (‘0001111010’) are used to
stuff the data stream. The CH7307C supports the following clock multipliers and fill patterns shown in Table 2.
2.1.4 Synchronization
Synchronization and channel-to-channel de-skewing is facilitated by the transmission of special characters during
the blank period. The CH7307C synchronizes during the initialization period and subsequently uses the blank
periods to re-synchronize to the data stream.
6
Pixel Rate
25~50 MP/s
50~100 MP/s
100~200 MP/s
Table 2: CH7307C supported Pixel Rates, Clock Rates, Data Transfer Rates and Fill Patterns
Input Interface
UNCTIONAL
Clock Rate – Multiplier
100~200 MHz – 4xPixel Rate
100~200 MHz – 2xPixel Rate
100~200 MHz – 1xPixel Rate
D
ESCRIPTION
Stuffing Format
Data, Fill, Fill, Fill
Data, Fill
Data
201-0000-062
1.00~2.00Gbits/s – 10xClock Rate
Data Transfer Rate - Multiplier
1.00~2.00Gbits/s – 10xClock Rate
1.00~2.00Gbits/s – 10xClock Rate
Rev. 1.4,
CH7307C
7/31/2008