gl845 Genesys Logic, gl845 Datasheet - Page 67

• Manufacturer Part Number: gl845
• Description: High Speed Usb 2.0 2-in-1 Scanner Controller With Adf
• Manufacturer: Genesys Logic

©2000-2007 Genesys Logic Inc. - All rights reserved.
Offset B8h ……..……..………………....………..…………..….………..…..…. Default value = 8’h00
7
6
3
2
1
0
Offset B9h ……..……..………………....………..…………..….………..…..…. Default value = 8’h00
7
6
5
4
5-0
5-4 TSH_SEL [1:0]
3
TCK_EN
ILX580
R/W
R/W
STOPPWM
ILX580
TSH_EN
SW2_EN
SW2_SEL
SW4_EN
SW4EXCHG
TCK_EN
TCK_SEL
TCK4_DIS
TCK3_DIS
TCK1_DIS
GL845 High Speed USB2.0 2-in-1 Scanner Controller With ADF
TCK_SEL TCK4_DIS TCK3_DIS TCK1_DIS
TSH_EN
[5:0]
R/W
R/W
Enable Sony ILX580 CCD timing
Enable Special CCD timing of CCD TG for Toshiba’s application
Select special CCD timing of CCD RS and CCD SW4 for Toshiba’s application
when TSH_EN is set to “1”
Enable special CCD timing of CCD SW2 for Toshiba’s application
0 CCD SW2 and CCD SW5 timing control is based on internal CCD_CNX
1 CCD SW2 and CCD SW5 timing control is based on internal SH_CNT
Enable special CCD timing of CCD SW4 for Toshiba’s application
Control CCD SW4 shutter for Multi-SH apllication
0 Select traditional CCD PHI clocks timing
1 Select special CCD PHI clocks timing such as NEC 8884 or Toshiba CCD
0 CCD PHI clocks timing is based on internal CCD_CNX counter of ASIC
1 CCD PHI clocks timing is based on internal SH_CNT counter of ASIC
0 Enable CCD PHI4 clock output when ASIC works on special CCD timing
1 Disable CCD PHI4 clock output when ASIC works on special CCD timing
0 Enable CCD PHI3 clock output when ASIC works on special CCD timing
1 Disable CCD PHI3 clock output when ASIC works on special CCD timing
0 Enable CCD PHI1 & 2 clocks output when ASIC works on special CCD
1 Disable CCD PHI1 & 2 clocks output when ASIC works on special CCD
Set the PWM control of motor driver IC during motor stopping.
counter of ASIC
counter of ASIC
operation
operation
operation
operation
timing operation
timing operation
TSH_SEL1 TSH_SEL0
R/W
R/W
R/W
R/W
SW2_EN
R/W
R/W
TSHMSKB2 TSHMSKB1 TSHMSKB0
SW2_SEL
R/W
R/W
SW4_EN
R/W
R/W
SW4EXCHG
Page 67
R/W
R/W