DS2149 MAXIM [Maxim Integrated Products], DS2149 Datasheet - Page 9

• Manufacturer Part Number: DS2149
• Description: 5V T1/J1 Line Interface Unit
• Manufacturer: MAXIM [Maxim Integrated Products]

3. INITIALIZATION AND RESET
During power-up, all control registers are cleared, disabling the transmitter outputs. The device requires a
master clock supplied to the MCLK input pin to operate the PLL. This master clock must be independent,
free-running, and jitter free.
A reset initializes the status and state machines for the RCL, AIS, NLOOP, and QRSS blocks. Under
software control, setting the RESET bit (CR2.7) clears all registers. Allow up to 100ms for the receiver to
recover from initialization.
4. REGISTER DEFINITIONS
The DS2149 contains eight registers for configuring the device and reading status. These are accessible
using the serial port.
Reading or writing to the internal registers requires writing one address/command byte prior to
transferring register data. The first bit written (LSb) of the address/command byte specifies whether the
access is a read (1) or a write (0). The next 6 bits identify the register address.
The last bit (MSb) of the address/command byte is the burst mode bit. When the burst bit is enabled (set
to 1) and a READ operation is performed, addresses 10h through 17h are read sequentially, starting at
address 10h. And when the burst bit is enabled and a WRITE operation is performed, addresses 10h
through 17h are written sequentially, starting at address 10h. Burst operation is stopped once address 17h
is read. All data transfers are initiated by driving the CS input low. All data transfers are terminated if the
CS input transitions high. Port control logic is disabled and SDO is tri-stated when CS is high.
Table 4-A. Register Map
Control Register 1
Control Register 2
Control Register 3
Interrupt Mask Register
Transition Status Register
Status Register
Information Register
Control Register 4
Table 4-B. Register Bit Positions
SYMBOL 7 (MSb)
Note: Set unused bits to 0 for normal operation.
IMR
CR1
CR2
CR3
TSR
CR4
SR
IR
REGISTER
JASEL1
RESET
JA6HZ
Z16D
Z16D
RL3
—
—
Table 4-A
JASEL0
PAT1
JALT
JALT
TPD
RL2
—
—
6
lists the register names and addresses.
SYMBOL
IMR
CR1
CR2
CR3
TSR
CR4
ENCENB
SR
IR
DFMO
DFMO
DFMO
PAT0
RL1
—
—
5
EQZMON20 EQZMON26
UNIENB
B8ZSD
B8ZSD
TAIS
RL0
9 of 32
—
—
4
ADDRESS
B010000
B010001
B010010
B010011
B010100
B010101
B010110
B010111
ENLOOP
QRSS
QRSS
QRSS
LUP
L3
—
3
RCL2048
JA128
ALB
LDN
AIS
AIS
AIS
L2
2
NLOOP
NLOOP
NLOOP
XFMR2
LIRST
TSCD
LLB
L1
1
XFMR1
0 (LSb)
TAOZ
LOTC
RLB
RCL
RCL
RCL
L0