DS1045 DALLAS [Dallas Semiconductor], DS1045 Datasheet
DS1045
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DS1045 Summary of contents
Page 1
... Each 4-bit programmable output offers the user 16 possible delay values to select from, starting with a minimum inherent DS1045 delay and a maximum achievable delay in the standard DS1045 family of 84 ns. The standard DS1045 product line provides the user with three devices having uniform delay increments and 5 ns, depending on the device ...
Page 2
... Figure 1. Parallel input A0-A3 and B0-B3 accept TTL levels and are used to set the delay values of outputs OUTA and OUTB, respectively. Sixteen possible delay values between the minimum 9 ns delay and the maxi-mum delay of the DS1045-x device version can be selected using the parallel programming inputs A0-A3 or B0-B3 (see Table 2, “Delay vs. Programmed Input”). For example, the DS1045-3 outputs OUTA or OUTB and can be programmed to produce 16 possible delays between the 9 ns (minimum) and the 54 ns (maximum increment levels ...
Page 3
... The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected to the output. The DS1045 parallel inputs are controlled by an interface to a central computer. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus ...
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... EDV SYMBOL MIN TYP TYP MAX UNITS 5.0 5. +0.5 0.8 A +1.0 A 35 (0°C to 70° 5%) CC MAX UNITS ns Table MAX UNITS 10 pF DS1045 NOTES NOTES 2 = 25°C) NOTES ...
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... Measurement Point = 1.5V on inputs and outputs Output Load Capacitance = 15 pF NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions. TIMING DIAGRAM: NON-LATCHED PARALLEL MODE TIMING DIAGRAM: LATCHED PARALLEL MODE DS1045 IH ...
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... TIMING DIAGRAM: DS1045 INPUTS TO OUTPUTS TERMINOLOGY PERIOD: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. t (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V WI point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V on the leading edge. ...