az100lvel16vt Arizona Microtek, Inc., az100lvel16vt Datasheet - Page 2

• Manufacturer Part Number: az100lvel16vt
• Description: Ecl/pecl Oscillator Gain Stage & Buffer With Selectable Enable
• Manufacturer: Arizona Microtek, Inc.

*Connections to V
EN-SEL
NC
NC
V
V
V
V
D/D ¯
Q/Q ¯
Q
V
EN-SEL
EN/EN
CS-SEL
V
V
V
EE
EE
EE
EE
HG
BB
EEP
EE
CC
AZ100LVEL16VT
left open (NC), the output current sources are disabled and the Q
is connected to V
resistor to connect V
MLP 8, 2x2 mm Package, VTNA, VTNB, VTNC & VTND Versions
operation. VTNA and VTNB utilize an enable (EN
LOW, the Q ¯ and Q
Q ¯
EN input is HIGH, the Q ¯ and Q
high and the Q ¯
resistors. In VTNB and VTNC, the D ¯ input is internally tied directly to the V
pin through a 470 Ω internal bias resistor. Bypassing V
disabled, while the Q ¯ output operates with a 4 mA current source to V
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
*
*
*
*
May 2008 * REV - 11
/Q ¯
PIN
¯¯
HG
HG
Outputs Q
All MLP 8, 2x2mm versions of the AZ100LVEL16VT provide an enable input that allows continuous oscillator
For VTNA and VTND, both D and D ¯ inputs are brought out and tied to the V
All MLP 8, 2x2mm versions (VTNA, VTNB, VTNC & VTND) have the Q, Q
output is forced low. VTNC and VTND utilize an enable (EN) that operates in the CMOS/TTL mode. When the
PECL Low, V
PECL High or V
CMOS Low or V
CMOS High or V
NC, no external pull-up
NC, with ≤20kΩ to V
Data Inputs
Data Outputs
Data Outputs w/High Gain
Reference Voltage Output
Selects Enable Logic
Enable Input
Selects Q and Q ¯ Current Source Magnitude
Optional Q
Negative Supply
Positive Supply
ENABLE TRUTH TABLE
HG
CC
HG
PIN DESCRIPTION
EE
or V
output is forced low.
and Q ¯
MLP 16 (VTL)
HG
, the current sources are activated. The Q
EN
EEP
/Q ¯
EE
EE
HG
HG
to V
HG
must be less than 1Ω.
or NC
CC
EE
and Q ¯
CC
each have an optional on-chip pull-down current source of 10 mA. When pad/pin V
outputs follow the data inputs. When EN
FUNCTION
EE
CC
. (See graph on page 5.)
HG
HG
/Q ¯
Current Sources
Data
Data
Data
Data
Data
Data
Q/Q ¯
HG
outputs follow the data inputs. When EN is LOW, the Q
www.azmicrotek.com
Data
High
High
Data
High
Data
Q
HG
¯¯ ) that operates in the PECL/ECL mode. When the EN
Q ¯
Data
Low
Low
Data
Low
Data
2
HG
BB
to ground with a 0.01 μF capacitor is recommended.
HG
/Q ¯
HG
¯¯ is HIGH, the Q
HG
THRESHOLD
CMOS / TTL
/Q ¯
pull-down current can be decreased, by using a
EE
HG
*Connections to V
NC
V
V
.
V
EN
470 ?
CURRENT SOURCE TRUTH TABLE
D
D
CS-SEL
Q
Q
operate as standard PECL/ECL. When V
BB
EE
CC
*
*
BB
pin and the D input is tied to the V
470 ?
BB
HG
4mA typ.
8mA typ.
0
MLP 16 (VTL)
pin through 470 Ω internal bias
MLP 16 (VTL)
HG
output is forced high and the
4mA EA.
CC
, and Q ¯
Q
or V
EE
HG
10mA EA.
HG
must be less than 1Ω.
4mA typ.
8mA typ.
4mA typ.
output is forced
current sources
¯¯ input is
Q ¯
EEP
CS-SEL
Q
Q
EN-SEL
V
V
EEP
HG
HG
EEP
BB
EE
is