ld7575b Leadtrend Technology, ld7575b Datasheet - Page 10

• Manufacturer Part Number: ld7575b
• Description: Green-mode Pwm Controller With High-voltage Start-up Circuit
• Manufacturer: Leadtrend Technology

Oscillator and Switching Frequency
Connecting a resistor from RT pin to GND according to the
equation can program the normal switching frequency:
The suggested operating frequency range of LD7575B is
within 50KHz to 130KHz.
Internal Slope Compensation
A fundamental issue of current mode control is the stability
problem when its duty-cycle is operated more than 50%. To
stabilize the control loop, the slope compensation is needed
in the traditional UC384X design by injecting the ramp signal
from the RT/CT pin through a coupling capacitor. In
LD7575B, the internal slope compensation circuit has been
implemented to simplify the external circuit design.
On/Off Control
The LD7575B can be controlled to turn off by pulling COMP
pin to lower than 1.2V. The gate output pin of LD7575B will
Leadtrend Technology Corporation
LD7575B-DS-00 May 2008
f
SW
=
RT
65
K (
0 .
Ω
)
×
100
(
KHz
)
Fig. 16
10
be disabled immediately under such condition. The off mode
can be released when the pull-low signal is removed.
Dual-Oscillator Green-Mode Operation
There
implemented in different chips for the green-mode or power
saving
“skipping-cycle Mode”, “variable off-time control “…etc. The
basic operation theory of all these approaches intended to
reduce the switching cycles under light-load or no-load
condition either by skipping some switching pulses or
reduce the switching frequency.
By using this dual-oscillator control, the green-mode
frequency can be well controlled and further to avoid the
generation of audible noise.
Over Load Protection (OLP)
To protect the circuit from the damage during over load
condition or short condition, a smart OLP function is
implemented in the LD7575B. Figure 17 shows the
waveforms of the OLP operation.
condition, the feedback system will force the voltage loop
toward the saturation and thus pull the voltage on COMP pin
(VCOMP) to high. Whenever the VCOMP trips the OLP
threshold 5.0V and keeps longer than 30mS (when
switching frequency is 65KHz), the protection is activated
and then turns off the gate output to stop the switching of
power circuit. The 30mS delay time is to prevent the false
trigger from the power-on and turn-off transient.
A divide-2 counter is implemented to reduce the average
power under OLP behavior. Whenever OLP is activated,
the output is latched off and the divide-2 counter starts to
count the number of UVLO(off).
the 2nd UVLO(off) point is counted then the output is
recovery to switching again.
By using such protection mechanism, the average input
power can be reduced to very low level so that the
component temperature and stress can be controlled within
the safe operating area.
are
requirements
many
difference
such
as
LD7575B
topologies
The latch is released if
“burst-mode
Under such fault
has
control”,
been