ld7576jps Leadtrend Technology, ld7576jps Datasheet - Page 15

• Manufacturer Part Number: ld7576jps
• Description: Green-mode Pwm Controller With High-voltage Start-up Circuit And Adjustable Olp Delay Time
• Manufacturer: Leadtrend Technology

Protection Resistor on the Hi-V Path
In some other Hi-V process and design, there may be a
parasitic SCR caused around HV pin, Vcc and GND. As
shown in figure 23, a small negative spike on the HV pin
may trigger this parasitic SCR and cause latchup between
Vcc and GND. It will intend to damage the chip because of
the equivalent short-circuit induced by such latchup
behavior.
Leadtrend’s proprietary of Hi-V technology will eliminate
parasitic SCR in LD7576X series. Figure 24 shows the
equivalent circuit of LD7576X series of Hi-V structure. So
that LD7576X series are more capable to sustain negative
voltage than similar products. However, a 10KΩ resistor is
recommended to be added on the Hi-V path to play as a
current limit resistor whenever a negative voltage is applied.
On-Chip OTP
An internal OTP circuit is embedded inside the LD7576/76J
to provide the worst-case protection for this controller. When
the chip temperature rises higher than the trip OTP level, the
Leadtrend Technology Corporation
LD7576-DS-03 December 2007
Fig. 23
Fig. 24
www.leadtrend.com.tw
15
output will be disabled until the chip is cooled down below
the hysteresis window.
On-Chip OTP – Latch - Mode
As similar behavior like OLP and OVP on Vcc latch-mode,
an
LD7576H/76K to provide the worst-case protection for this
controller. When the chip temperature rises higher than the
trip OTP level, it shutdowns the output gate drive circuit
simultaneously to latch off the switching of the power
MOSFET. It won’t recover unless the chip is cooled down
below the OTP threshold and recycle again.
Latch-Mode Protection
The latch-mode protection in LD7576 series will be enabled
by pulling the CT pin voltage below 0.8V. Figure 26 shows
the operation. When the latch-mode is tripped, LD7576
series will shutdown the gate output and then latch-off the
power supply. Unless the controllers re-plug and re-start to
drop VCC below 8V, the gate output mode will remain
latched. The detailed operation is depicted as figure 26.
internal
OTP
LD7576/76H/76J/76K
circuit
Fig. 26
are
embedded
with
the