UPD16680P NEC [NEC], UPD16680P Datasheet - Page 38

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UPD16680P

Manufacturer Part Number
UPD16680P
Description
1/53, 1/40 DUTY, LCD CONTROLLER/DRIVER WITH BUILT-IN RAM
Manufacturer
NEC [NEC]
Datasheet
Required conditions for timing (Unless otherwise specified, T
1. Common
Remark The TYP. value is a reference value when T
2. Serial interface
Note See 11.1.3 Transmission (Command/Data read).
3. Parallel interface
38
Clock frequency
High-level clock pulse width
Low -level clock pulse width
High-level clock pulse width
Low -level clock pulse width
Rise/Fall time
Reset pulse width
Shift clock cycle
High-level shift clock pulse width
Low-level shift clock pulse width
Shift clock hold time
Data setup time
Data hold time
STB hold time
STB pulse width
Wait time
Enable cycle time
High-level enable pulse width
Low-level enable pulse width
STB pulse width
STB hold time
Enable hold time
Data setup time
Data hold time
Note
Parameter
Parameter
Parameter
t
t
t
t
t
t
t
t
t
Synbol
Symbol
CYK
WHK
WLK
HSTBK
DS1
DH1
HKSTB
WSTB
WAIT
Symbol
t
t
t
t
t
f
WHC1
t
t
t
t
t
WHC2
WLC2
WLC1
WRE
CYCE
t
t
WSTB
HKSTB
HSTBK
t
t
OSC
r
, t
WHE
WLE
DS2
DH2
f
OSC
OSC
OSC
OSC
OSC
OSC
/RESET pin
SCK
SCK
SCK
STB
DATA
SCK
SCK
8th CLK
E
E
E
D
D
0
0
Data Sheet S12694EJ2V0DS00
to D
to D
IN
IN
IN
BRI
BRI
BRI
external clock
external clock
external clock
E
external clock
external clock
external clock
7
7
SCK
SCK
DATA
STB
A
1st CLK
E
E
=+25 C.
Conditions
Conditions
Conditions
A
= –40 to +85 C, V
MIN.
900
295
295
210
400
400
MIN.
MIN.
40
40
400
400
900
295
295
400
400
210
100
20
40
40
10
10
50
DD
= 2.7 to 3.3 V)
TYP.
TYP.
TYP.
32
MAX.
MAX.
MAX.
100
50
25
25
Unit
PD16680
ns
ns
ns
ns
ns
ns
ns
ns
Unit
kHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s

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