ov9625 ETC-unknow, ov9625 Datasheet - Page 4

• Manufacturer Part Number: ov9625
• Description: Ov9625 Color Cmos Sxga Mpixel Camerachip Ov9121 Cmos Sxga Mpixel Camerachip
• Manufacturer: ETC-unknow

OV9625/OV9121
Figure 5 Pixel Array
Figure 6 Sub-Sampling Mode
4
Row #
Sub-sampling Mode
Default resolution for the OV9625/OV9121 is 1280 x 1024
pixels, with all active pixels being output (see
The OV9625/OV9121 can be programmed to output in
640 x 480 (VGA) sized images for applications where
higher resolution image capture is not required.
For VGA resolution, the following sub-sampling method is
available:
Progressive Sub-sampling
The entire array is sub-sampled for maximal image
quality.
sub-sampled to an aspect ration of 4:2 as illustrated in
Figure
Row
n+1
n+2
n+3
n+4
n+5
n+6
n+7
6.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n
Both
n
Column
Proprietary to OmniVision Technologies
B
G
B
G
B
G
B
G
i
B
G
B
G
i+1
horizontal
G
R
G
R
G
R
G
R
Skipped Pixels
G
R
G
R
i+2 i+3 i+4 i+5 i+6 i+7 i+8 i+9
B
G
B
G
B
G
B
G
CMOS SXGA (1.3 MPixel) C
G
R
G
R
G
R
G
R
Column #
B
G
B
G
and
B
G
B
G
B
G
B
G
G
R
G
R
G
R
G
R
G
R
G
R
vertical
B
G
B
G
B
G
B
G
B
G
B
G
G
R
G
R
G
R
G
R
G
R
G
R
pixels
B
G
B
G
B
G
B
G
Figure
G
R
G
R
G
R
G
R
are
5).
AMERA
Slave Operation Mode
Figure 7 Slave Mode Connection
Figure 8 Slave Mode Timing
Channel Average Calculator
VSYNC
HSYNC
C
MCLK
NOTE:
1) T
2) T
3) T
HIP
The OV9625/OV9121 can be programmed to operate in
slave mode (default is master mode).
When used as a slave device, the OV9625/OV9121
changes the HSYNC and VSYNC outputs to input pins for
use as horizontal and vertical synchronization input
triggers supplied by the master device. The master device
must provide the following signals:
1.
2.
3.
See
detailed timing considerations. In this mode, the clock for
all devices should be the same. Otherwise, the devices
will suffer from flickering at line frequency.
OV9625/OV9121 provides average output level data for
the R/G/B channels along with frame-averaged luminance
level. Access to the data is via the serial control port.
Average values are calculated from 128 pixels per line (64
in VGA).
HS
line
frame
™
Figure 7
> 6 T
= 1520 x T
System clock MCLK to XCLK1 pin
Horizontal sync MHSYNC to CHSYNC pin
Vertical frame sync MVSYNC to VSYNC pin
= 1050 x T
clk
, Tvs > T
CHSYNC
(OV9121)
OV9625
VSYNC
for slave mode connections and
XCLK1
T
D[9:0]
clk
VS
line
(SXGA); T
line
(SXGA); T
T
T
line
Version 1.3, September 15, 2003
clk
T
frame
line
frame
= 800 x T
MHSYNC
MVSYNC
MCLK
= 500 x T
Master
Device
clk
(VGA)
line
O
T
(VGA)
Figure 8
mni
HS
ision
for