ch7028b Chrontel, ch7028b Datasheet - Page 9

• Manufacturer Part Number: ch7028b
• Description: Chrontel Ch7028b Sdtv Encoder
• Manufacturer: Chrontel

CHRONTEL
Table 2: Pin Name Descriptions (LQFP64 Package)
209-1000-001
Pin #
41 - 56
59 - 60
62
61
63
4
3
5
31
32
22
20
24
28
29
Type
In
I/O
I/O
In
In
In
In
I/O
In
Out
Out
In
In
Out
Rev. 1.1,
Symbol
D[17:0]
V
H/WEB
DE/CSB
AS
ATPG
ResetB
SPD
SPC
DAC0
DAC1
ISET
XI
XO
08/21/2008
[1]
Description
Data[0] through Data[17] Inputs
These pins accept the 18 data inputs from a digital video port of a
graphics controller. The swing is defined by VDDIO.
Vertical Sync Input / Output
When the SYO control bit is low, this pin accepts a vertical sync input
for use with the input data.
When the SYO control bit is high, the device will output a vertical sync
pulse. The output is driven from the VDDIO supply.
Horizontal Sync Input / Output
When the SYO control bit is low, this pin accepts a horizontal sync input
for use with the input data.
When the SYO control bit is high, the device will output a horizontal
sync pulse. The output is driven from the VDDIO supply.
It is also the WEB signal of CPU/MEMERY interface.
Data Input Indicator
When the pin is high, the input data is active.
When the pin is low, the input data is blanking.
CSB signal input of CPU/MEMERY interface.
Serial Port Device Address Select
0: 76h
1: 75h
ATPG Enable (Internally pull-down)
This pin should be left open or pulled low with a 10k resistor in the
application. This pin configures the pre-condition for scan chain and
boundary scan test when high. Otherwise it should be pulled low.
Voltage level is 0 to 3.3V.
Reset * Input
When this pin is low, the device is held in the power-on reset condition.
When this pin is high, reset is controlled through the serial port.
Serial Port Data Input / Output (open drain)
This pin functions as the bi-directional data pin of the serial port.
External pull-up resister is required.
Serial Port Clock Input (open drain)
This pin functions as the clock pin of the serial port. External pull-up
resister is required.
CVBS or S-video output
Full swing is up to 1.3v.
CVBS or S-video output
Full swing is up to 1.3v.
Current Set Resistor Input
This pin sets the DAC current. A 1.2k
be connected between this pin and AGND_DAC using short and wide
traces.
Crystal Input / External Input
For some situation of the slave mode, a parallel resonance crystal (± 20
ppm) should be attached between this pin and XO.
external 3.3V CMOS compatible clock can drive the XI/FIN input.
Crystal Output
For some situation of the slave mode, a parallel resonance crystal (± 20
Ω
, 1% tolerance resistor should
CH7028B
However, an
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