vt82c586a ETC-unknow, vt82c586a Datasheet - Page 11

• Manufacturer Part Number: vt82c586a
• Description: Integrated Peripheral Controller
• Manufacturer: ETC-unknow

PWRGD
PCIRST#
RSTDRV
BCLK
OSC
CPURST
INTR
NMI
INIT
STPCLK#
SMI#
FERR#
IGENN#
PCLK
FRAME#
AD[31:0]
C/BE[3:0]#
IRDY#
TRDY#
STOP#
DEVSEL#
PAR
SERR#
IDSEL
PIRQA-D#
PREQ#
Preliminary Revision 0.1 October 13, 1996
Signal Name

194, 182, 173,
204-199, 196-
195, 192-189,
187-185, 183,
172, 170-167,
165-163, 161-
158, 155-152
1, 207-205
Pin No.
138
142
145
146
143
148
149
141
139
181
162
180
179
176
178
174
175
193
151
14
4
6
3
2
I/O
O
O
O
O
O
O
O
O
O
O
O
O
B
B
B
B
B
B
B
B
I
I
I
I
I
I
Power Good. Connected to the POWERGOOD signal on the Power Supply.
PCI Reset. An active low reset signal for the PCI bus. The VT82C586A will
generate PCIRST# during power-up or from the control register.
Reset Drive. RSTDRV is the reset signal to the ISA bus.
Bus Clock. ISA bus clock.
Oscillator. OSC is the 14.31818 MHz clock signal. It is used by the internal 8254.
CPU Reset. The VT82C586A asserts CPURST to reset the CPU during power-up.
CPU Interrupt. INTR is driven by the VT82C586A to signal the CPU that an
interrupt request is pending and needs service.
Non-Maskable Interrupt. NMI is used to force a non-maskable interrupt to the
CPU. The VT82C586A generates an NMI when either SERR# or IOCHK# is
asserted.
Initialization. The VT82C586A asserts INIT if it detects a shut-down special cycle
on the PCI bus or if a soft reset is initiated by the register
Stop Clock. STPCLK# is asserted by the VT82C586A to the CPU in response to
different Power-Management events.
System Management Interrupt. SMI# is asserted by the VT82C586A to the CPU
in response to different Power-Management events.
Numerical Coprocessor Error. This signal is tied to the coprocessor error signal on
the CPU.
Ignore Error. This pin is connected to the “ignore error” pin on the CPU.
PCI Clock. PCLK provides timing for all transactions on the PCI Bus.
Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates
that one more data transfer is desired by the cycle initiator.
Address/Data Bus. The standard PCI address and data lines. The address is driven
with FRAME# assertion and data is driven or received in following cycles.
Command/Byte Enable. The command is driven with FRAME# assertion. Byte
enables corresponding to supplied or requested data are driven on following clocks.
Initiator Ready. Asserted when the initiator is ready for data transfer.
Target Ready. Asserted when the target is ready for data transfer.
Stop. Asserted by the target to request the master to stop the current transaction.
Device Select. VT82C586A asserts this signal to claim PCI transactions through
positive or subtractive decoding.
Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]#.
System Error. SERR# can be pulsed active by any PCI device that detects a system
error condition. Upon sampling SERR# active, the VT82C586A can be programmed
to generate an NMI to the CPU.
Initialization Device Select. IDSEL is used as a chip select during configuration
read and write cycles.
PCI Interrupt Request.
PCI Request. This signal goes to the VT82C595. It is the VT82C586A’s request
for the PCI bus.
Table 1. Pin Descriptions
PCI Bus Interface
Reset and Clock
CPU Interface
-5-
Signal Description
VT82C586A
Pinouts