ax88790 ASIX Electronics Corporation, ax88790 Datasheet - Page 17

• Manufacturer Part Number: ax88790
• Description: Pcmcia 10/100m Fast Ethernet Controller With Embedded Phy
• Manufacturer: ASIX Electronics Corporation

The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to access the
LAN specific registers (MAC Core Registers).
I/O Base Register 0
I/O Base Register 1
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)
FIELD
FIELD
FIELD
7:3
7:0
7:0
2
1
0
AX88790 L
R/W/C
R/W/C
R/W/C
R/W
R/W
R/W
R
R
-
Reserved
PPwrDwn : PHY power down setting
While this bit set to 1, AX88790 will force embedded PHY into power down mode. As for
PPWDN is active high or active low. Please refer section 2.9 Power on configuration setup
signal cross-reference table.
Note: The master control of Power Down mode is place on Bit 0 of CFL. If user want to
enable power down mode, must set the relative bit of EEPROM that map to bit 0 of CFL
register to logic 1. When this bit is set to 1, the LAN will go into power down mode. At
power down mode AX88790 will disable MAC transmitting and receiving operation. But
the host interface will not be affected.
Intr: Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
IntrAck: Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
Base I/O address bit 7 – 0.
Base I/O address bit 15 – 8.
3-in-1 PCMCIA Fast Ethernet Controller
17
DESCRIPTION
DESCRIPTION
DESCRIPTION
ASIX ELECTRONICS CORPORATION