sh6636 SinoWealth Micro-Electronics Corp. Ltd, sh6636 Datasheet - Page 10

• Manufacturer Part Number: sh6636
• Description: Mask 4-bit Microcontroller With Remote Control Carrier Synthesizer
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

8. Interrupt
Two interrupt sources are available on the SH6636:
- Timer0 overflow interrupt
- Port's falling edge detection interrupt ( PBC )
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program.
Those flags are cleared to 0 at initialization by the chip reset.
When IEx is set to 1 and the interrupt request is generated (IRQx is 1), the interrupt will be activated and a vector address will
be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into the stack memory and jump to the interrupt service vector address. After the interrupt occurs, all interrupt enable
flags (IEx) are reset to 0 automatically, so when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and the vector
address will be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Servicing Sequence Diagram:
Interrupt Nesting:
During the SH6610C CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt.
The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is
ready and the instruction of execution, N is IE enabled, then the interrupt will start immediately after the next two instruction
executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will
be terminated.
(a) Timer (Timer0) Interrupt
The timer overflow will generate an internal interrupt request, when the counter counts overflow from $FF to $00. If the interrupt
enable flag is enabled, then a timer interrupt service routine will start. This can also be used to wake the CPU from HALT mode.
Address
Inst. cycle
$00
$01
Interrupt Generated
Bit3
-
-
Instruction
Execution
N
1
IRQT0
IET0
Bit2
Interrupt Accepted
Instruction
Execution
I1
2
Bit1
-
-
Vector Generated
Stacking
Instruction
Execution
10
I2
3
IRQP
Bit0
IEP
Fetch Vector address
Reset IE.X
4
Start at vector address
Interrupt request flags
Interrupt enable flags
5
Remarks
SH6636