sh66l06a SinoWealth Micro-Electronics Corp. Ltd, sh66l06a Datasheet - Page 11

• Manufacturer Part Number: sh66l06a
• Description: 1k 4-bit Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

8. Interrupt
Four interrupt sources are available on SH66L06A:
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program.
Those flags are clear to “0” at initialization by the chip reset.
System Register:
When IEx is set to “1” and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are cleared to “0” automatically, so when IRQx is 1 and IEx is set to “1” again, the interrupt will be activated and vector address
will be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Nesting
During the CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt. The servicing
sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the
instruction of execution N is IE enabled, then the interrupt will start immediately after the next two instruction executions.
However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be
terminated.
External Interrupt
When Bit3 of system register $00 (IEX) is set to “1”, the external interrupt will be enabled, and a low level applying on the
external interrupt I/O port will generate an external interrupt. External Interrupt can be used to wake the CPU from HALT or
STOP mode.
Timer Interrupt
The input clocks of Timer0 and Timer1 are based on system clock source. The timer overflow from $FF to $00 will generate an
internal interrupt request (IRQT0 or IRQT1 = 1), If the interrupt enable flag is enabled (IET0 or IET1 = 1), a timer interrupt
service routine will start. Timer interrupt can also be used to wake the CPU from HALT mode.
Port Low Active Interrupt
Only the digital input port can generate a port interrupt. The analog input cannot generate an interrupt request.
Any one of the I/O input port applying with a low level would generate an interrupt request (IRQP = 1). In order to avoid
multi-responses, it is strongly recommended that the relative input port cannot be connected with a low level all the time. Port
Interrupt can be used to wake the CPU from HALT or STOP mode.
- External interrupt (Low active)
- Timer0 interrupt
- Timer1 interrupt
- PORTB interrupt (Low active)
Address
$00
$01
Inst.cycle
IRQX
Bit 3
IEX
Interrupt Generated
IRQT0
Bit 2
IET0
Instruction
Execution
1
N
IRQT1
Bit 1
IET1
Interrupt Servicing Sequence Diagram
Interrupt Accepted
Instruction
Execution
2
I1
IRQP
Bit 0
IEP
R/W
R/W
R/W
Vector Generated
11
Instruction
Execution
Stacking
I2
3
Fetch Vector address
Interrupt request flags register
Interrupt enable flags register
Reset IE.X
4
Remarks
Start at vector address
5
SH66L06A