sh66l10a SinoWealth Micro-Electronics Corp. Ltd, sh66l10a Datasheet - Page 11

• Manufacturer Part Number: sh66l10a
• Description: 2k 4-bit Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

7. Timer
SH66L10A has two 8-bit timers.
The timer/counter has the following features:
The following is a simplified timer block diagram.
The timers provide the following functions:
7.1. Timer0 and Timer1 Configuration and Operation
Both the Timer0 and Timer1 consist of an 8-bit write-only
timer load register (TL0L, TL0H; TL1L, TL1H) and an 8-bit
read-only timer counter (TC0L, TC0H; TC1L, TC1H). Each of
them has both low-order digits and high-order digits. Writing
data into the timer load register (TL0L, TL0H; TL1L, TL1H)
can initialize the timer counter.
7.2. Timer0 and Timer1 Mode Register
The timer can be programmed in several different prescalers by setting Timer Mode register (T0M, T1M).
The clock source pre-scale by the 8-level counter first, then generate the output plus to timer counter. The Timer Mode registers
(T0M, T1M) are 3-bit registers used for the timer control as shown in Table 1 and Table 2.
Table 1: Timer0 Mode Register ($02)
- 8-bit up-counting timer/counter.
- Automatic re-load counter.
- 8-level prescaler.
- Interrupt on overflow from $FF to $00.
- Programmable interval timer function.
- Read counter value.
T0M.2 T0M.1 T0M.0
System
clock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
TM.2
Prescaler
t
TM.1
osc
0
1
0
1
0
1
0
1
TM.0
SYNC
Divide Ratio
Prescaler
/2
/2
/2
/2
/2
/2
/2
/2
11
COUNTER
9
7
5
3
2
1
0
8-BIT
Clock Source
System clock
System clock
System clock
System clock
System clock
System clock
System clock
System clock
11
The low-order digit should be written first, and then the
high-order digit. The timer/counter is automatically loaded
with the contents of the load register when the high-order
digit is written or counter counts overflow from $FF to $00.
Timer Load Register: The register H controls the physical
READ and WRITE operations.
Please follow these steps:
Write Operation:
Read Operation:
Table 2: Timer1 Mode Register ($03)
T1M.2 T1M.1 T1M.0
0
0
0
0
1
1
1
1
Low nibble first
High nibble to update the counter
High nibble first
Low nibble followed.
0
0
1
1
0
0
1
1
Load Reg. L
Latch Reg. L
0
1
0
1
0
1
0
1
8-bit timer counter
Divide Ratio
Prescaler
Load Reg. H
/2
/2
/2
/2
/2
/2
/2
/2
11
9
7
5
3
2
1
0
SH66L10A
Clock Source
System clock
System clock
System clock
System clock
System clock
System clock
System clock
System clock