sh66p51 SinoWealth Micro-Electronics Corp. Ltd, sh66p51 Datasheet - Page 9

• Manufacturer Part Number: sh66p51
• Description: Otp 2k 4-bit Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

2. RAM
Built-in RAM contains general-purpose data memory and system register. Because of its static nature, the RAM can keep
data after the CPU enters STOP or HALT.
2.1. RAM Addressing
Data memory and system register can be accessed in one instruction by direct addressing. The following is the memory
allocation map:
System register and I/O: $000 - $027
Data memory: $028 - $0A7
LCD RAM space: $300 - $33A
2.2. Configuration of System Register:
Address
$0C
$0D
$0A
$0B
$0E
$0F
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$10
$11
$12
$13
$14
$15
$16
$17
$18
PULLEN
PACR.3
BTM.3
TBR.3
TH0.3
DPL.3
TL0.3
INX.3
PC.3
PD.3
O/S1
PAIN
PA.3
PB.3
OXS
Bit3
-
-
-
-
-
-
-
-
-
-
PACR.2
LCDON
DPM.2
IRQT0
BTM.2
DPH.2
TM0.2
TBR.2
DPL.2
TH0.2
TL0.2
CPS2
INX.2
O/S0
PBIN
PB.2
PC.2
PD.2
IET0
PA.2
Bit2
-
-
-
-
-
PACR.1
DUTY1
DPM.1
IRQBT
DPH.1
TM0.1
BTM.1
TBR.1
TH0.1
DPL.1
TL0.1
CPS1
INX.1
PCIN
IEBT
PC.1
PD.1
OXM
PA.1
PB.1
PE.1
Bit1
-
-
-
-
PACR.0
DUTY0
REMO
DPM.0
BTM.0
DPH.0
OXON
TM0.0
TBR.0
DPL.0
TH0.0
TL0.0
INX.0
CPS0
IRQP
PDIN
PEIN
PB.0
PC.0
PD.0
PE.0
REM
PA.0
Bit0
LPD
IEP
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
9
Interrupt enable flags
Timer0 Mode register
Timer0 load/counter register low digit
Timer0 load/counter register high digit
PORTB
Bit0: REMO output data
Bit0: REM pin output status
Table Branch Register
Pseudo index register
Data pointer for INX low nibble
Data pointer for INX middle nibble
Data pointer for INX high nibble
Bit2 - 0: Carrier counter source pre-divider
Bit3: Port pull-high enable control
Bit0: Turn on OSCX oscillator
Bit1: CPU clocks select (1: OSCX/0: OSC)
Bit3: OSCX type selection
Bit0, 1: Select LCD DUTY (1/3 or 1/4 or 1/5 or 1/6)
Bit2: Set PORTC as LCD Segment1 - 4
Bit3: Set PORTD as LCD Segment5 - 8
Control PORTA - PORTD input and output access enable
or disable. Used in key matrix’s application
Control PORTE input and output access enable or disable.
Used in key matrix’s application
PORTA input/output control
Interrupt request flags
Base Timer Mode register
Bit0: 2.3V LPD flag
Bit2: Set LCD display ON
PORTA
PORTC
PORTD
PORTE
Remarks
SH66P51