sh66p31b SinoWealth Micro-Electronics Corp. Ltd, sh66p31b Datasheet - Page 14

• Manufacturer Part Number: sh66p31b
• Description: Otp 1k 4-bit Micro-controller
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

8. Interrupt
Two interrupt sources are available on SH66P31B:
- Timer0 interrupt
- PORTA, B, C interrupts (Falling edge)
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the program.
Those flags are clear to “0” at initialization by the chip reset.
System Register:
When IEx is set to “1” and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are clear to “0” automatically, so when IRQx is 1 and IEx is set to “1” again, the interrupt will be activated and vector address will
be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Nesting:
During the CPU interrupt service, user can enable any interrupt enable flag before returning from the interrupt. The servicing
sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is ready and the
instruction of execution N is IE enabled, then the interrupt will start immediately after the next two instruction executions.
However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will be
terminated.
Timer Interrupt
The input clocks of Timer0 are based on system clock or external clock/event T0 input as Timer0 source. The timer overflow
from $FF to $00 will generate an internal interrupt request (IRQT0 = 1), If the interrupt enable flag is enabled (IET0 = 1), a timer
interrupt service routine will start. Timer interrupt can also be used to wake the CPU from HALT mode.
Port Falling Edge Interrupt
Only the digital input port can generate a port interrupt. The analog input cannot generate an interrupt request.
Any one of the I/O input pin transitions from V
transition would not be able to make a new interrupt request until all of the input pins have returned to V
used to wake the CPU from HALT or STOP mode.
Address
$00
$01
Bit 3
-
-
Inst.cycle
IRQT0
Bit 2
IET0
Interrupt Generated
Instruction
Execution
1
N
Bit 1
-
-
Interrupt Servicing Sequence Diagram
DD
Interrupt Accepted
Instruction
IRQP
Execution
Bit 0
to GND would generate an interrupt request (IRQP = 1). Further falling edge
IEP
I1
2
R/W
W
W
14
Vector Generated
Instruction
Execution
Stacking
3
I2
Fetch Vector address
Reset IE.X
Interrupt request flags
4
Interrupt enable flags
Remarks
Start at vector address
5
DD
. Port Interrupt can be
SH66P31B