sh66k12 SinoWealth Micro-Electronics Corp. Ltd, sh66k12 Datasheet - Page 4

• Manufacturer Part Number: sh66k12
• Description: Mask 4-bit Microcontroller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

3. RAM
Built-in RAM contains of general-purpose data memory, LCD
RAM, and system register. Data memory, LCD RAM, and
system register can be direct accessed by in one instruction
cycle. Because of its static nature, the RAM can keep data
after the CPU enters STOP or HALT.
(a) Data memory, LCD RAM, and System register
The following is the memory allocation map:
$000 - $01F: System register and I/O
$020 - $11F: Data memory (256 X 4 bits divided into 2
$300 - $319: LCD RAM space (26 X 4 bits)
(c) Configuration of System Register
$16 - $1F
Address
$0C
$0D
$0A
$0B
$0E
$0F
$00
$02
$03
$04
$05
$06
$07
$08
$09
$10
$11
$12
$13
$14
$15
$01
banks)
TBR.3
T0H.3
T1H.3
DPL.3
T0L.3
T1L.3
AEC3
IRQX
LPD3
INX.3
Bit 3
PA.3
PB.3
PC.3
PD.3
O/S
IEX
-
-
-
-
-
-
-
LCDOFF
IRQT0
DPM.2
DPH.2
T0M.2
T1M.2
TBR.2
T0H.2
T1H.2
DPL.2
AEC2
T0L.2
T1L.2
LPD2
INX.2
PC.2
PD.2
Bit 2
IET0
PA.2
PB.2
-
-
-
DPM.1
IRQT1
T0M.1
T1M.1
TBR.1
DPH.1
T0H.1
T1H.1
DPL.1
AEC1
T0L.1
T1L.1
LPD1
INX.1
PC.1
PD.1
Bit 1
IET1
PA.1
PB.1
HLM
B1
-
-
DPM.0
DPH.0
T0M.0
T1M.0
TBR.0
DPL.0
DUTY
T0H.0
T1H.0
AEC0
T0L.0
T1L.0
LPD0
INX.0
IRQP
PC.0
PD.0
Bit 0
PA.0
PB.0
PAM
IEP
B0
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4
W
R
-
(b) Data Pointer
The Data Pointer can indirectly address data memory.
Pointer address is located in register DPM (3-bits) and DPL
(4-bits). The addressing range can have 128 locations.
Pseudo index address (INX) is used to read or write Data
memory, and then RAM address bit9-bit0 comes from DPH,
DPM and DPL.
Interrupt enable flags
Interrupt request flags
Bit0-2: Timer0 Mode register
Bit0-2: Timer1 Mode register
Timer0 load/counter register low nibble
Timer0 load/counter register high nibble
Timer1 load/counter register low nibble
Timer1 load/counter register high nibble
PORTA
PORTB
PORTC
PORTD
LPD Enable Control (LPD3 - 0):
0101: LPD Enable (Default);
1010: LPD Disable
Bonding option
Table Branch Register
Pseudo index register
Data pointer for INX low nibble
Data pointer for INX middle nibble
Data pointer for INX high nibble
Bit0: set PA.1, PA.2 as Alarm output
Bit1: HEAVY LOAD Mode
Bit2: LCD off or LCD on
Bit3: set LCD segment as output
Alarm Envelope Control
Bit0: change LCD duty to 1/4 duty, 1/3 bias
Reserved
Description
SH66K12