sh66k33a SinoWealth Micro-Electronics Corp. Ltd, sh66k33a Datasheet - Page 13

• Manufacturer Part Number: sh66k33a
• Description: Mask 1k 4-bit Micro-controller
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

10. Low Voltage Reset (LVR)
The LVR function monitors the supply voltage and applies an internal reset in the micro-controller at battery replacement. If the
applied circuit satisfies the following conditions, the LVR can be incorporated by the software control.
The software enable flag controls LVR circuit on/off.
LVR circuit operating ambient temperature is T
Functions of LVR Circuit:
The LVR circuit has the following functions:
Generates an internal reset signal when V
Cancels the internal reset signal when V
Stops the oscillator operation and forces the CPU to enter STOP mode when V
As V
then cancel the LVR reset.
LVR Control Register:
11. Watchdog Timer (WDT)
The watchdog timer is a 16-bit count-down counter, and its clock source is an independent built-in RC oscillator. But it will not
run in the STOP mode. The watchdog timer automatically generates a device reset when it overflows. To prevent it timing out
and generating a device reset condition, users should write watchdog timer reset bit ($14 bit3) as “1” before timing-out. The
watchdog timer has a time-out period of approx. 16ms.
System Register $14 (WDT)
Note:
The WDT bit is cleared only if the Watchdog Timer time-out occurred both in normal operation mode and in the HALT mode.
The watchdog timer is cleared when the device wakes up from the STOP mode, regardless of the source of wake-up.
12. HALT and STOP Mode
After the execution of HALT instruction, SH66K33A will enter HALT mode. In HALT mode, the CPU will stop operating. But
peripheral circuit (timer) will keep status.
After the execution of STOP instruction, SH66K33A will enter STOP mode. In STOP mode, the whole chip (including oscillator)
will stop operating. But watchdog is still enabled.
In HALT mode, SH66K33A can be waked up if any interrupt occurs.
In STOP mode, SH66K33A can be waked up if port interrupt occurs.
When CPU is awaked from the HALT/STOP by any interrupt source, it will execute the relevant interrupt serve subroutine at
first. Then the instruction next to halt/stop is executed.
Address
Address
$14
$15
DD
≦ V
LVR
WDT
Bit 3
LVR3
, the LVR reset will delay about 1ms before being triggered. If V
Bit3
Bit 2
LVR2
Bit2
-
Bit 1
LVR1
Bit1
-
DD
DD
> V
≦ V
A
LVR
= -10 ℃ to +70 ℃
Bit 0
LVR.
LVR0
.
-
Bit0
R/W
R/W Bit3: Watchdog timer reset bit (Write “1” to reset WDT)
13
R/W
R/W
LVR Enable Control (LVR3 - 0):
1010: LVR Disable
Else: LVR Enable (Power-on initial 0000)
DD
DD
goes back to V
≤ V
LVR
.
Remarks
Remarks
DD
> V
LVR
, without any delay
SH66K33A