sh6611a SinoWealth Micro-Electronics Corp. Ltd, sh6611a Datasheet - Page 8

• Manufacturer Part Number: sh6611a
• Description: 1k 4-bit Microcontroller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

7.Interrupt
Four interrupt sources are available on SH6611A:
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Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 and $01 of the system register. They can be accessed or tested by the
program. Those flags are cleared to 0 at initialization by the chip reset.
When IEx is set to 1 and the interrupt request is generated (IRQx is 1), the interrupt will be activated and vector address will
be generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag
will be saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable
flags (IEx) are reset to 0 automatically, so when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and vector
address will be generated from the priority PLA corresponding to the interrupt sources.
External Interrupt ( INT )
External interrupt is shared with the bit0 of PORTA. When bit3 of system register 0 (IEX) is set to 1, the external interrupt
will be enabled, and a falling edge signal on PA.0 will generate an external interrupt. (Note: while external interrupt is
enabled, writing a "0" to bit0 of PORTA will generate an external interrupt).
Port falling edge Interrupt
The PortB are used as port interrupt sources. Any one of the PortB pin transitions from VDD to GND would generate an
interrupt request (IRQP=1). Further falling edge transition would not be able to make a new interrupt request until all of the
input pins have returned to VDD. Port Interrupt can be used to wake the CPU from HALT or STOP mode.
Timer Interrupt
The input clock of Timer0 and Timer1 are based on system clock. The timer overflow from $FF to $00 will generate an
internal interrupt request (IRQT0 or IRQT1=1), If the interrupt enable flag is enabled (IET0 or IET1=1), a timer interrupt
service routine will start. Timer interrupt can also be used to wake the CPU from HALT mode.
Interrupt Nesting:
During the SH6610C CPU interrupt service, the user can enable any INTERRUPT enable flag before returning from the
interrupt. The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the
interrupt request is ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the
next two instruction executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then
the interrupt service will be terminated.
Interrupt Servicing Sequence Diagram:
Inst.cycle
Address
$00
$01
External interrupt ( INT shared with PA.0)
Timer0 interrupt
Timer1 interrupt
PortB interrupts (falling edge)
IRQX
Bit 3
IEX
Interrupt Generated
Instruction
Execution
1
N
IRQT0
Bit 2
IET0
IRQT1
Bit 1
IET1
Interrupt Accepted
Instruction
Execution
2
I1
IRQP
Bit 0
IEP
R/W
R/W
R/W
Vector Generated
Instruction
Execution
8/25
Stacking
3
I2
Interrupt request flags
Interrupt enable flags
Fetch Vector address
Reset IE.X
Remark
4
Start at vector address
5
SH6611A
Ver 0.0