dq8051 Digital Core Design, dq8051 Datasheet - Page 2

• Manufacturer Part Number: dq8051
• Manufacturer: Digital Core Design

80C51
DQ8051
DQ8051+DPTRs
DQ8051+DPTRs+SXDM
DQ8051+DPTRs+SXDM+MDU32
●
●
●
rameter is real application speed improvement
comparing to well known 80C51 architecture. The
Dhrystone Benchmark Version 2.1 was used to
measure 80C51 and DQ8051 core performance.
The following table gives a survey about the
DQ8051 performance in terms of Dhrystone VAX
MIPS per 1 MHz and its improvement comparing
to 80C51.
25
20
15
10
ters
with no internal tri‐states
One of the most important performance pa‐
5
0
Interface for additional Special Function Regis‐
Fully synthesizable, static synchronous design
Scan test ready
VAX MIPS ratio
Core performance in terms of DMIPS per MHz
P E R F O R M A N C E
1
Device
80C51
DQ8051
DQ8051+DPTRs
DQ8051+DPTRs+SXDM
DQ8051+DPTRs+SXDM+MDU32
19,69
23,77
All trademarks mentioned in this document are trademarks of their respective owners.
25,13
DMIPS/MHz
0,00941
0,18527
0,22369
0,23650
0,25053
Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
26,62
Ratio
19,69
23,77
25,13
26,62
1,00
DQ8051 core area in ASICs Devices (CPU features
and peripherals have been included):
DQ8051 core area and performance in ASIC devices. Results given for
working system with two DPTRs and connected 256B IDM, 8kB CODE
and 2kB SXDM memories.
vendor specific technologies is summarized in ta‐
ble below.
*CPU – consisted of ALU, Opcode Decoder, Control Unit, User SFRs interface,
IDM interface, XDM interface and Code Memory interface.
●
0,35 um
0.25 um
0.18 um
0.13 um
0.09 um
CPU*
DPTR1 register
DPTR0 decrement
DPTR1 decrement
DPTR’s auto‐switch and auto‐update
SXDM
Interrupt Controller
Power Management Unit
I/O ports
Timers
UART0
Total area
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○
○
○
The following tables give a survey about the
Area utilized by the each unit of DQ8051 core in
Device
DoCD™ debug unit
Processor execution control
Read‐write all processor contents
Code execution breakpoints
Hardware execution watch‐points at
○
○
○
○
○
○
○
○
○
○
○
Run, Halt
Step into instruction
Skip instruction
Program Counter (PC)
Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
two real‐time PC breakpoint
unlimited number of real‐time OPCODE breakpoints
Internal (direct) Data Memory
P E R I P H E R A L S
Core components area utilization
Component
Speed
typical
typical
typical
typical
typical
10500 gates
11000 gates
10500 gates
10700 gates
9900 gates
Min area
125 MHz
180 MHz
260 MHz
430 MHz
70 MHz
F
Area
[Gates]
max
7250
9900
400
150
150
200
700
800
50
50
75
75