msm8128vlmb-85 MOSA electronics corp., msm8128vlmb-85 Datasheet - Page 3

• Manufacturer Part Number: msm8128vlmb-85
• Description: 128k Sram
• Manufacturer: MOSA electronics corp.

MSM8128 - 70/85/10/12
Parameter
V
Data Retention Current
Chip Deselect to Data Retention t
Operation Recovery Time
Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,
The table below shows the logic inputs required to control the MSM8128 SRAM.
Low V
AC Test Conditions
Operating Modes
CC
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* V
for Data Retention
cc
=5V±10%
cc
Mode
Not Selected
Not Selected
Output Disable
Read
Write
Data Retention Characteristics - L Version Only (T
Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,
CS2 must be
high impedance state.
1 = V
V
IH
,
CC
CS1 CS2
- 0.2V or 0V
X
0
1
0
0
Symbol Test Condition
V
I
t
X
0
1
1
1
CCDR
CDR
R
DR
0 = V
OE
CS2
X
X
X
1
0
CS1
0V
V
CS2
See Retention Waveform
See Retention Waveform
CC
IL
,
=3.0V,V
CS2
WE
0.2V. The other input levels (address, WE,OE,I/O) can be in the
V
V
X
X
1
1
0
CC
CC
-0.2V or 0V
X = Don't Care
-0.2V, CS2
IN
0.2V. V
V
0V, CS1
CC
I
I
SB1
SB
Output Load
Current
I
I
I
,I
CC
CC
CC
IN
,I
SB1
SB2
I/O Pin
A
0V
V
CS2
=-55°C to +125
CC
V
-0.2V or
CC
-0.2V,
0.2V.
I/O Pin
High Z
High Z
High Z
D
D
OUT
IN
30pF
166
o
C)
2.0
min
Reference Cycle
1.76V
0
5
-
Power Down
Power Down
Read Cycle
Write Cycle
typ
-
-
-
-
Issue 4.5 : April 2001
max
660
-
-
-
Unit
V
ns
ms
A