msm80c85ahrs Oki Semiconductor, msm80c85ahrs Datasheet - Page 22

• Manufacturer Part Number: msm80c85ahrs
• Description: 8-bit Cmos Microprocessor
• Manufacturer: Oki Semiconductor

¡ Semiconductor
SUPPLEMENTARY EXPLANATION
(1) SIM instruction: The execution of the SIM instruction uses the contents of the accumulator
(2) RIM instruction: When the contents of the accumulator are read out after RIM instruction has
to mask MSM80C85AH’S interrupts.
been executed, MSM80C85AH interrupt status can be known.
R7.5 (Reset interrupt 7.5 Flip-flop): When this bit is set to 1, the edge detecting flip-flop
of RST 7.5 interrupt is reset.
MSE (Mask Set Enable): When this bit is set to 1, the interrupt mask bits are valid.
M7.5 (Mask RST7.5): When this bit is set to 1 and MSE bit is set to 1, RST7.5 interrupt is
masked.
M6.5 (Mask RST6.5): When this bit is set to 1 and MSE bit is set to 1, RST6.5 interrupt is
masked.
M5.5 (Mask RST5.5): When this bit is set to 1 and MSE bit is set to 1, RST 5.5 interrupt is
masked.
17.5 (Pending RST7.5): When RST7.5 interrupt is pending, "1" is read out.
16.5 (Pending RST6.5): When RST6.5 interrupt is pending, "1" is read out.
15.5 (Pending RST5.5): When RST5.5 interrupt is pending, "1" is read out.
IE (Interrupt Enable Flag): When interrupt is Enable, "1" is read out.
M7.5 (Mask RST7.5): When RST7.5 interrupt is masked, "1" is read out.
M6.5 (Mask RST6.5): When RST6.5 interrupt is masked, "1" is read out.
M5.5 (Mask RST5.5): When RST5.5 interrupt is masked ,"1" is read out.
Accumulator Setting Value
Accumulator Reading Value
Bit 7
Bit 7
—
—
17.5
—
6
6
16.5
—
5
5
R7.5
15.5
4
4
MSE
IE
3
3
M7.5
M7.5
2
2
M6.5
M6.5
1
1
MSM80C85AHRS/GS/JS
M5.5
M5.5
0
0
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