bt848kpf ETC-unknow, bt848kpf Datasheet - Page 130

• Manufacturer Part Number: bt848kpf
• Description: Single-chip Video Capture For Pci
• Manufacturer: ETC-unknow

C
Timing Generator Load Byte
Timing Generator Load Byte
Memory Mapped Location 0x080 – (TGLB)
Upon reset, it is initialized to 00.
Timing Generator Control
Memory Mapped Location 0x084 – (TGCTRL)
Upon reset, it is initialized to 00.
120
Bits
Bits
ONTROL
Notes: (1). Since the entire decoder will be running off the external clock GPCLK, when selecting the GPCLK is activat-
[7:0]
[4:3]
[6:5]
0
1
2
7
R
EGISTER
Type
Type
ed, the decoder functionality is subject to a halt condition if the input port is disconnected. A clock detect circuit
will allow the decoder to fall back on either the PLL or the Xtal, whichever is enabled via PLL_I. If the PLL has
been put to sleep, then the decoder will fall back on the Xtal0 input. The VPRES status condition indicates the
status of the clock detect output when in digital video input mode which is monitoring GPCLK.
Note that it is desirable for SW to set up the PLL to run at the same frequency as the GPCLK input, so if the
digital camera is disconnected, then blue-field timing will run properly.
RW
RW
RW
RW
RW
RW
–
D
Default
00
Default
00
IGITAL
V
IDEO
Name
TGLB
Name
TGC_VM
GPC_AR
TGC_AI
TGCKI
TGCKO
Reserved
I
N
S
UPPORT
(B
T
848A/849A O
Description
Load SRAM 1 byte at a time, in sequence after a TGC_AR. Load
the least significant byte first. Each write to this address causes an
automatic advance of the SRAM byte location.
TGC_AI bit must be pulsed by s/w in order for the SRAM byte loca-
tion to advance.
Description
Timing Generator Video Mode enable.
Timing Generator Address Reset.
Timing Generator Read Address Increment -active hi pulse incre-
ments the read address.
Decoder Input Clock Select.
GPCLK Output Clock Select
Must be written with a logical zero.
Reading from this address only reads the current byte. The
0
1
00
01
10
11
00
01
10
11
L848A_A
= Read/write mode
= Enable timing generator/read mode
= Normal xtal 0/xtal 1 mode
= PLL
= GPCLK
= GPCLK - inverted
= CLKx1
= xtal 0 input
= PLL
= PLL - inverted
NLY
)
(1)
(1)
Single-Chip Video Capture for PCI
Bt848/848A/849A
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