lp62s16128b-i AMIC Technology Corporation, lp62s16128b-i Datasheet - Page 10

• Manufacturer Part Number: lp62s16128b-i
• Description: 128k X 16 Bit Low Voltage Cmos Sram
• Manufacturer: AMIC Technology Corporation

Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
Notes: 1. t
(June, 2004, Version 1.4)
DATA OUT
DATA IN
Address
HB, LB
2. A Write occurs during the overlap (t
3. t
4. OE level is high or low.
5. Transition is measured ± 500Mv from steady state. This parameter is sampled and not 100% tested.
WE
CE
WR
AS
is measured from the address valid to the beginning of Write.
is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle.
t
AS
t
1
WHZ
4
WP
, t
BW
) of a low CE , WE and ( HB and, or LB ).
t
AW
t
WC
9
t
WP
t
t
BW
CW
2
t
DW
LP62S16128B-I Series
AMIC Technology, Corp.
t
WR
3
t
t
OW
DH