km641001a Samsung Semiconductor, Inc., km641001a Datasheet
km641001a
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km641001a Summary of contents
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... KM641001A Document Title 256Kx 4 High Speed Static RAM(5V Operating), Evolutionary Pin Out. Operated at Commercial Temperature Range. Revision History Rev. No. History Rev. 0.0 Initial release with Design Target. Rev. 1.0 Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary Rev. 2.0 Release to final Data Sheet. 2.1. Delete Preliminary Rev ...
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... The KM641001A is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The KM641001A uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG s advanced CMOS process and designed for high-speed circuit technology ...
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... KM641001A ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... OLZ OHZ PRELIMINARY CMOS SRAM Value 3ns 1.5V See below , t & t OLZ OHZ +5.0V 480 OUT 5pF* KM641001A-20 Unit Min Max - ...
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... (Address Controlled CS=OE (WE OLZ t LZ(4,5) Valid Data PRELIMINARY CMOS SRAM KM641001A-20 Unit Min Max Valid Data t HZ(3,4,5) t OHZ t ...
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... KM641001A NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to HZ ...
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... KM641001A TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; ...
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... KM641001A PACKAGE DIMENSIONS 28-SOJ-400A #28 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 +0.004 0.017 -0.002 0. 0.0375 #15 #14 18.82 MAX 0.741 18.41 0.12 0.725 0.005 1.27 ( 0.050 1.32 ( 0.052 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 - 8 - PRELIMINARY CMOS SRAM Units:millimeters/Inches 9.40 0.25 0.370 0.010 +0.10 0.20 -0.05 +0.10 0.008 -0.002 0.69 MIN 0.027 ) 3.76 0.10 MAX MAX 0.148 0.004 ) Rev 5.0 February 1998 ...