k9k1208u0m-ycb0 Samsung Semiconductor, Inc., k9k1208u0m-ycb0 Datasheet - Page 5

• Manufacturer Part Number: k9k1208u0m-ycb0
• Description: 64m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PIN DESCRIPTION
Command Latch Enable(CLE)
Address Latch Enable(ALE)
Chip Enable(CE)
Write Enable(WE)
Read Enable(RE)
I/O Port : I/O 0 ~ I/O 7
Write Protect(WP)
Ready/Busy(R/B)
K9K1208U0M-YCB0, K9K1208U0M-YIB0
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid t
of RE which also increments the internal column address counter by one.
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
GND (Pin # 6)
Connect this input pin to GND or set to static low state unless the sequential read mode excluding spare area is used.
5
FLASH MEMORY
REA
after the falling edge