z86l0408ssc ZiLOG Semiconductor, z86l0408ssc Datasheet - Page 14

• Manufacturer Part Number: z86l0408ssc
• Description: Z8 8-bit Cost-effective Microcontrollers
• Manufacturer: ZiLOG Semiconductor

Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer func-
tion. The POR time allows V
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the five
following conditions:
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an on-
board RC oscillator. If the permanent WDT option is select-
ed then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be dis-
abled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
14
Power bad to power good status
Stop-Mode Recovery
WDT time-out
WDT time-out (in HALT Mode)
WDT time-out (in STOP Mode)
CC
and the oscillator circuit to
P R E L I M I N A R Y
Addr Reg.
FF
FE
FD
FC
FB
FA
F9
F8*
F7*
F6*
F5
F4
F3
F2
F1
Notes:
*Registers are not reset after a STOP-Mode Recovery using P27
pin. A subsequent reset will cause these control registers to be
reconfigured as shown in Table 4 and the user must avoid bus
contention on the port pins or it may affect device reliability.
SPL
GPR
RP
FLAGS U U U U U U U U
IMR
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
PRE1
T1
TMR
Table 3. Control Register Reset Values
D7 D6 D5 D4 D3 D2 D1 D0 Comments
U U 0
U U U U U U U U
U U U 0 U U 0
U U U U U U 0
U U U U U U U 0
U U U U U U U U
U U U U U U 0
U U U U U U U U
0
0
0
0 U U U U U U U
1
0
0
0
0
1
0
Reset Condition
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0 IRQ3 is used
1
0 P2 open-drain
1 Inputs after
0
0
DS97LVO0901
for positive
edge
detection
reset
Zilog