rf2052 RF Micro Devices, rf2052 Datasheet - Page 11

• Manufacturer Part Number: rf2052
• Description: High Performance Wideband Rf Synthesizer/vco With Integrated Rf Mixer
• Manufacturer: RF Micro Devices

Hardware Control
Three hardware control pins are provided: ENBL, MODE and RESETB. ENBL will enable the part when asserted high. This
enables all circuitry except for the digital, which is always active providing a power supply is present. If the CFG3:REFSTBY bit is
not set, ENBL will also control the activation of the XO and biasing circuitry. IF CFG3:REFSTBY bit is asserted high, the XO and
biasing circuitry will always be active.
The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The
device includes a POR function, so this pin should not normally be required, in which case it should be connected to the posi-
tive supply.
The MODE pin controls which mixer and PLL programming register block is active.
Calibration
Two calibration functions are included in the device; a frequency calibration function and a VCO tuning gain calibration func-
tion.
The frequency calibration is enabled using the PLL1x0:P1_CT_EN and PLL2x0:P2_CT_EN control words. When enabled, the
calibration is performed whenever ENABLE is asserted. The device will perform a coarse tuning function whereby fixed capaci-
tance elements are progressively connected to the VCO resonant circuit until the VCO is oscillating at approximately the correct
frequency. The output of this calibration is made available in the RB1:CT_CAL read-back register. A value of 128 or 0 in this
register indicates that the coarse tune was unsuccessful. This will only occur if the user is trying to program a frequency that is
outside of the VCO operating range. A value between 0 and 128 indicates a successful calibration, and will be dependent on
the desired frequency, as well as process variation for a particular device. The calibration operation takes approximately 50 μ s.
If start-up time is a critical parameter, and the user is always programming the same frequency for the PLL, the calibration
result may be read back from the RB1:CT_CAL register, and written to the PLL1x2:P1_CT_DEF or PLL2x2:P2_CT_DEF registers
(depending on desired programming block). The calibration function may then be disabled using the PLL1x0:P1_CT_EN or
PLL2x0:P2_CT_EN control words.
The VCO tuning gain calibration is enabled using the PLL1x1:P1_KV_EN or PLL2x1:P2_KV_EN registers. The tuning gain of the
VCO will vary according to the desired oscillation frequency (see performance graphs). When the synthesizer is only required to
generate a narrow range of frequencies, it is sufficient to simply look up the tuning gain of the VCO for that frequency range,
and design the loop filter accordingly. However, if a wide range of frequencies is required, there is some risk that the variation
in tuning gain will result in an unacceptable variation in the PLL loop bandwidth and may even result in loop instability. The tun-
ing gain calibration will compensate for VCO tuning gain variation by modifying the charge pump current such that the ratio
between the tuning gain and the charge pump current remains constant. This calibration requires approximately 100 μ s. The
result of the calibration will be returned to the RB1:CP_CAL read-back register. The charge pump current may be controlled
directly by the user by disabling the calibration using the PLL1x1:P1_KV_EN or PLL2x1:P2_KV_EN registers and writing the
required value to the PLL1x0:P1_CP_DEF or PLL2x0:P2_CP_DEF registers.
Prelim DS080513
SDATA
SCLK
ENX
t
EH
Serial Bus Read
t
X
ES
t
EH
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support, contact RFMD at ([phone] or [e-mail].
> 20ns, t
write
read
Preliminary
t
DS
RFSlice latches on
ES
A6
rising edge
>20ns, t
DS
>20ns, t
data on rising edge
RFSlice sets up
A0
t
DH
DH
Turnaround
1.5 Clock
> 20ns, t
t
CWH
D15
CWH
data on falling edge
Baseband latches
> 40ns, t
D14
t
CWL
CWL
>40ns
D0
t
EH
RF2052
t
ES
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