rf2057 RF Micro Devices, rf2057 Datasheet - Page 11

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rf2057

Manufacturer Part Number
rf2057
Description
High Performance Wideband Rf Pll/vco With Integrated Rf Mixers For Repeaters
Manufacturer
RF Micro Devices
Datasheet

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Fractional-N PLL
The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the VCO. The PLL includes automatic
calibration systems to counteract the effects of process and environmental variations, ensuring repeatable lock-time and noise
performance. The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. A reference divider (divide by 1 to
divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a maximum of 52MHz. The
reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set high for divider
bypass (divide by 1). The remaining three bits CLK DIV<15:13> set the reference divider value, divide by 2 (010) to 7 (111)
when the reference divider is enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RF2057 these banks are used to program mixer 1 and mixer 2 respectively, and are selected automatically
as the mixer is selected (using the MODE pin).
The PLL will lock the VCO to the frequency F
where N
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, N
N(9:0) should be set to the integer part of N
Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is:
The N value is set to 92, equal to the integer part of N
by 2
Converting N and NUM into binary results in the following:
So the registers would be programmed:
The maximum N
for a 23.92MHz reference, the frequency step size would be 1.4Hz. The minimum reference frequency that could be used to
program a frequency of 2400MHz is 2400/511, 4.697MHz (approx).
DS091109
24
:
EFF
is the programmed fractional N divider value, F
EFF
is 511, and the minimum N
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N
EFF
P1_NUM_MSB (or P2_NUM_MSB)=1100 1111 0011 0010
=F
VCO
NUM=0.80936454849 * 2
NUM=1100 1111 0011 0010 1000 0100
P1_NUM_LSB (or P2_NUM_LSB)=1000 0100
EFF
VCO
*R / F
. NUM should be set to the fractional part of N
EFF
according to:
P1_N (or P2_N)=0 0101 1100
OSC
is 15, when in fractional mode. The minimum step size is F
F
N
=2220 *1 / 23.92=92.80936454849.
EFF
VCO
N=0 0101 1100
EFF
EFF
, and the NUM value is set to the fractional portion of N
=N
=F
:
OSC
VCO
EFF
*F
is the reference input frequency, and R is the programmed R
*R/F
OSC
24
OSC
/R
=13,578,884.
EFF
multiplied by 2
RF2057
OSC
24
/R*2
=16777216.
EFF
multiplied
24
11 of 38
. Thus

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