V3025 EMMICRO [EM Microelectronic - MARIN SA], V3025 Datasheet - Page 10

• Manufacturer Part Number: V3025
• Description: 17Very Low Power 8-Bit 32 kHz RTC Module with Digital Trimming, User RAM and Battery Switch-over
• Manufacturer: EMMICRO [EM Microelectronic - MARIN SA]

Pin Description
SO28 Package
Functional Description
Power Supply, Data Retention and Standby
The V3025 is put in standby mode by activating the PFI
input. When pulled logic low, PFI will disable the input
lines, and immediately take to high impedance the lines
AD 0-7. Input states must be under control whenever
provided, PFI can be tied to the system RESET . Even
in standby the interrupt request pin IRQ will pull to ground
upon an unmasked alarm interrupt occurring.
Switch-over
The switch-over supplies the core of the RTC. The I/O
pads are supplied by V
The SYNC input is internally pulled-up to V
be externally pulled-up between 2 and 5.5V. The switch-
over circuitry works in recovery mode. During switching,
both transistors (V
This is to guarantee that the RTC is always supplied. The
power fail signal becomes active ( PFO = 0) when V
V
Copyright © 2004, EM Microelectronic-Marin SA
PFI is deactivated. If no specific power fail signal can be
Pin
1
2
3
4
5
6
7
8
9
10-14
15-19
20
21
22
23
24
25
26
27
28
BAT
(see Table 4).
Name
AD0
AD1
AD2
AD3
V
V
V
AD4
AD5
AD6
AD7
V
PFI
IRQ
PFO
RD
SYNC
A /D
CS
WR
OUT
SS
DD
BAT
R
DD
Description
Time synchronization
Power fail
Bit 0 from MUX address /
data bus
Bit 1 from MUX address /
data bus
Bit 2 from MUX address /
data bus
Bit 3 from MUX address /
data bus
Address / data decode
Interrupt request
Switch-over output
Supply ground (substrate)
Positive supply terminal
Power fail output
Chip select
(Motorola)
Bit 4 from MUX address /
data bus
Bit 5 from MUX address /
data bus
Bit 6 from MUX address /
data bus
Bit 7 from MUX address /
data bus
Battery supply
RD (Intel) or DS (Motorola)
WR (Intel) or R/ W
to V
DD
OUT
, except for IRQ and SYNC .
and V
BAT
to V
OUT
OUT
, IRQ can
) are ON.
Table 5
PWR
PWR
GND
DD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
I
I
I
<
Initialisation
When power is first applied to the V3025 all registers have
a random value.
To initialise the V3025, software must first write a 1 to the
initialisation bit (addr. 2 bit 4) and then a 0. This sets the
Frequency Tuning bit and clears all other status bits.
The time and date parameters should then be loaded into
the RAM (addr. 20 to 28 hex) and then transferred to the
reserved clock area using the clock command followed by
a write.
The digital trimming register must then be initialised
by writing 210 (D2 hex) to it, if Frequency Tuning is
not required.
digital trimming register the frequency tuning mode
bit can be cleared.
RAM Configuration
The RAM area of the V3025 has a reserved clock and
time area, a data space, user RAM and an address
command space (see Table 10 or Fig. 10). The reserved
clock and timer area is not directly accessible to the user,
it is used for internal time keeping and contains the
current time and date plus the timer parameters.
Data Space
All locations in the data space are Read/Write. The data
space is directly accessible to the user and is divided into
five areas:
Status Registers – three registers used for status and
control data for the device (see Table 7, 8 and 9).
Reserved bits must be set to 0.
Digital Trimming Register – a special function described
under "Frequency Tuning".
Time and Date Registers – 9 time and date locations
which are loaded with, either the current time and date
parameters from the reserved clock area or the time and
date parameters to be transferred to the reserved clock
area.
Alarm Registers – 5 locations used for setting the alarm
parameters.
Timer Registers – 4 locations which are loaded with
either the timer parameters from the reserved timer area
or the timer parameters to be transferred to the reserved
timer area.
User RAM
The V3025 has 16 bytes of general purpose RAM
available for the users applications. This RAM block is
located at addresses 50 to 5F hex and is maintained even
in the standby mode ( PFI active). The commands, or the
time set lock bit, have no effect on the user RAM block.
Reading or writing to the user RAM is similar to reading or
writing to any system RAM address.
10
After having written a value to the
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V3025