lxt6155 Intel Corporation, lxt6155 Datasheet - Page 27

• Manufacturer Part Number: lxt6155
• Description: 155 Mbps Sdh/sonet/atm Transceiver
• Manufacturer: Intel Corporation

Datasheet
Bit
Bit
4:1
7
6
5
4
3
2
1
0
7
6
5
0
Table 8.
Table 9.
Default
Default
0.1.1.1
0
0
0
0
1
1
0
0
1
1
0
1
.
Primary Control Register Settings, Register #0 (Address A<3:0>=0000)
Tx Control, Register #1 (Address A<3:0>=0001)
tx_clk_sw_ena
tx_dig_reset
tx_amp_trim
Mnemonic
Mnemonic
media_sel
lpbk_cntl
sys_int
clk_inv
tx_ena
pll_ref
-
Local loopback:
0 = No loopback
1 = Activate local loopback
Remote loopback:
0 = No loopback
1 = Activate remote loopback
PLL/Equalizer reference clock control:
0 = Use TPICLK clock
1 = Use external crystal (XTALIN)
Not used
T
0 = TPID <7:0> sampled on the rising edge of TPICLK
1 = TPID <7:0> sampled on the falling edge of TPICLK
R
0 = RPOD <7:0> transitions on the rising edge of RPOCLK
1 = RPOD <7:0> transitions on the falling edge of RPOCLK
Systems interface mode selection:
0 = Serial mode
1 = Parallel 8 bit mode
Media and line code selection:
0 = Fiber (NRZ)
1 = Coax (CMI)
Tx output enable:
0 = outputs disabled
1 = outputs active
Tx digital circuitry reset. This can be used to minimize power comsumption when
the device is disabled but not powered down. It must be enabled when the device
is active.
0 = reset
1 = active
Transmit amplitude trim:
0000 = -21%
1111 = +24%
Tx clock detection enable. This must be disabled in SW mode when pll_ref=0
(reg#0<5>=0)
0 = disable
1 = enable
PICLK
POCLK
polarity at system interface:
polarity at system interface:
155 Mbps SDH/SONET/ATM Transceiver — LXT6155
Description
Description
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