zl10353qcg1 Zarlink Semiconductor, zl10353qcg1 Datasheet
zl10353qcg1
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zl10353qcg1 Summary of contents
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... Copyright 2005, Zarlink Semiconductor Inc. All Rights Reserved. Fully Compliant NorDig Unified COFDM Digital Terrestrial TV (DTV) Demodulator Ordering Information ZL10353QCG 64 Pin LQFP ZL10353QCG1 64 Pin LQFP* Trays, Bake & Drypack ZL10353QCF 64 Pin LQFP ZL10353QCF1 64 Pin LQFP* Tape & Reel,Bake & Drypack *Pb Free Matte Tin ...
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... Users have access to all the relevant signal quality information, including input signal power level, signal-to-noise ratio, pre-Viterbi BER, post-Viterbi BER, and the uncorrectable block counts. The error rate monitoring periods are programmable over a wide range. The device is packaged 64-pin LQFP and is very low power. ZL10353 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Pin & Package Details 1.1 Pin Outline Figure 2 below shows the basic, non-diversity, pin functions of the ZL10353. The device can effectively be set up in seven different pin configurations, so for brevity only this version is shown. ZL10353 Figure 2 - Pin Outline 3 Zarlink Semiconductor Inc. Data Sheet ...
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... MOVAL/DvVal Table 1 - Pin Names - Numeric Function Pin Function 43 PLLTEST 6 PLLVdd 49 RESET 50 RFLEV 51 SADD0 52 SADD1 53 SADD2/Dv0/Dv1 56 SADD3/Dv1/Dv3 Table 2 - Pin Names - Alphabetical Order 4 Zarlink Semiconductor Inc. Data Sheet Function Pin Function 49 MDO0/Dv0/ Dv1 50 MDO1/Dv1/ Dv3 51 MDO2/Dv2 52 MDO3/Dv3/ Dv1 53 MDO4/Dv4/ Dv0 54 Vdd 55 Vss 56 MDO5 ...
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... MPEG packet start MPEG/diversity data valid MPEG/diversity data bus MPEG/diversity clock out Block error MPEG clock in Status output or diversity data Interrupt output or diversity data Serial clock Serial data 5 Zarlink Semiconductor Inc. Data Sheet Pin Pin Function 12 Vss 25 10 Vss 38 44 Vss ...
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... PLL analogue test O positive input I negative input I RF level I PLL supply S S Core logic power S I/O ring power S Core and I/O ground S ADC analog supply S S 2nd ADC supply S 6 Zarlink Semiconductor Inc. Data Sheet Type mA V 3.3 3.3 CMOS 3.3 3.3 3.3 3 Open drain ...
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... Reed-Solomon decoders are equipped with bit-error monitors. The former provides the bit error rate (BER) at the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting intervals of these are programmable over a very wide range. ZL10353 Figure 3 - OFDM Demodulator Diagram 7 Zarlink Semiconductor Inc. Data Sheet ...
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... Slope control bits have been provided for the AGCs and these have to be set correctly depending on the gain-versus-voltage slope of the gain control amplifiers. ZL10353 Figure 4 - FEC Block Diagram 8 Zarlink Semiconductor Inc. Data Sheet ...
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... The FFT module uses the trigger information from the timing synchronization module to set the start point for an FFT. It then uses either FFT to transform the data from the time domain to the frequency domain. An extremely hardware-efficient and highly accurate algorithm has been used for this purpose. ZL10353 9 Zarlink Semiconductor Inc. Data Sheet ...
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... The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de-interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions to the FEC in the original order. ZL10353 10 Zarlink Semiconductor Inc. Data Sheet ...
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... MPEG data as uniformly spaced as possible to the transport processor. This frequency depends on the guard ratio, constellation, hierarchy and code rate. There is also an option for the data to be extracted from the ZL10353 with a clock provided by the user. ZL10353 11 Zarlink Semiconductor Inc. Data Sheet A trace-back This ...
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... The ZL10353 has a General Purpose Port that can be configured to provide a secondary 2-wire bus. See register GPP_CTL address 0x8C. Master control mode is selected by setting register SCAN_CTL (0x62) [b3 The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2. ZL10353 ADDR[3] ADDR[2] ADDR[1] SADD[2] SADD[1] SADD[0] VDD VDD VDD 12 Zarlink Semiconductor Inc. Data Sheet ...
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... S DEVICE R A DATA ADDRESS (reg n) t LOW HD;DAT HIGH SU;DAT HD;STA Figure 5 - Primary 2-Wire Bus Timing 13 Zarlink Semiconductor Inc. Data Sheet W Write (= 0) R Read (= 1) NA NOT Acknowledge RADD Register Address DATA NA P (reg n+ SU;STO SU;STA ...
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... The rise time depends on the external bus pull up resistor. Loading prevents full speed operation. ZL10353 Symbol f CLK t BUFF t HD;STA t LOW t HIGH t SU;STA t HD;DAT t SU;DAT SU;STO Table 3 - Timing of 2-Wire Bus 14 Zarlink Semiconductor Inc. Data Sheet Value Unit Min. Max 400 kHz 200 ns 200 ns 1300 ns 600 ns 200 ns 100 ns 100 ns 2 note ns ...
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... ZL10353 188 byte packet output 184 Transport packet bytes 4 bytes MDO[0] 15 Zarlink Semiconductor Inc. Data Sheet 1st byte 2nd byte ...
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... Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80 Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10 MOCLK frequency = 45.06 MHz. ZL10353 188 byte packet n Tp Figure 7 - MPEG Output Data Waveforms o C, Output load = 10pF Output load = 10pF. 16 Zarlink Semiconductor Inc. Data Sheet 1st byte packet n+1 Ti ...
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... The hold time is better when MOCLKINV = 1, therefore this should be used if possible. MOCLK MDO } MOSTRT MOVAL BKERRB BKERR ZL10353 Units Minimum 1.0 10 Figure 8 - MPEG Timing - MOCLKINV = 1 Delay conditions Units Minimum 1.0 20 Figure 9 - MPEG Timing - MOCLKINV = 0 17 Zarlink Semiconductor Inc. Data Sheet ...
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... IDD P core IDD C XTI 16.00 4 fCLK Symbol Min. Max. VDD -0.3 +3.6 CVDD -0.3 +2.0 VI -0.3 VI -0.3 VDD + 0.3 VO -0.3 VO -0.3 VDD + 0.3 TSTG -55 150 TOP -10 TJ 125 18 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units 3.0 3.3 3.6 1.8 1. 170 mA 20.48 25.00 MHz 400 kHz -10 80 Unit ...
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... SLEEP, OSCMODE GPP(3:0), CLK1, Vin +5.5V DATA1, RESET All inputs SLEEP, SMTEST, MICLK, CLK1, OSCMODE SADD(4:0), DATA1, GPP(3:0) 20.4800 MHz ± 150 ppm ± 200 ppm 27 pF 0.4 mW max <25 19 Zarlink Semiconductor Inc. Data Sheet Symbol Min. Typ. Max. VDD 3.0 3.3 3.6 CVDD 1.62 1.8 1.98 IDDCORE 170 300 VOH 2 ...
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... V operation -typical Rf 2 internal feedback resistor ESR maximum equivalent series resistance of crystal - given by crystal manufacturer ( ) f fundamental frequency of crystal (Hz) ZL10353 XTI XT0 XTI C1 C2 Figure 10 - Crystal Oscillator Circuit + out Zarlink Semiconductor Inc. Data Sheet OSCMODE 4pF. ...
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... L does not fall outside the crystal pulling range or the circuit may fail to start the crystal manufacturer who can then cut a crystal to order which will L 21 Zarlink Semiconductor Inc. Data Sheet = ...
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... V and and 22 k resistors) must be 800 mV < VCM < CVDD and the amplitude XTO XTI 36k 100k 10nF 22k 10nF in series with XTI or XTO may be required to limit the current taken from 22 Zarlink Semiconductor Inc. Data Sheet Vdd OSCMODE ...
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... Application Circuit ZL10353 Figure 12 - Typical Application Circuit 23 Zarlink Semiconductor Inc. Design Manual ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...