mt9315ap Zarlink Semiconductor, mt9315ap Datasheet
mt9315ap
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mt9315ap Summary of contents
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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ ...
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... MD2 L inear/ Rout /A-Law Limiter VSS VDD PWRDN DS5038 MT9315AP MT9315AE • Handles acoustic echo return loss and 0dB line ERL • Transparent data transfer and mute options • 20 MHz master clock operation • Low power mode during PCM Bypass Applications • ...
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MT9315 1 ENA1 2 MD1 ENA2 3 4 MD2 5 Rin PDIP Sin 6 7 VSS 8 MCLK LAW 13 FORMAT 14 PWRDN Pin Description Pin # Name 1 ENA1 SSI Enable Strobe ...
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Advance Information Pin Description (continued) Pin # Name 13 FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both serial pcm ports. 14 PWRDN Power-down (Input). An active ...
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MT9315 Functional Description The MT9315 device contains two echo cancellers, as well as the many control functions necessary to operate the echo cancellers. One canceller is for acoustic speaker to microphone echo, and one for line echo cancellation. The MT9315 ...
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Advance Information 4 Howling Detector (HWLD) (4. Patent Pending) The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. The HWLD can be disabled by setting the ...
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MT9315 Power Down Forcing the PWRDN pin to logic low, will put the MT9315 into a power down state. In this state all internal clocks are halted, the DATA1, Sout and Rout pins are tristated. The user should hold the ...
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Advance Information Sign-Magnitude FORMAT=0 PCM Code /A-LAW -LAW LAW = LAW = 0 + Full Scale 1111 1111 1000 0000 + Zero 1000 0000 1111 1111 - Zero 0000 0000 0111 1111 - Full Scale 0111 1111 ...
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MT9315 C4i F0i PORT1 Rin Sout PORT2 Sin ...
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Advance Information C4i F0i 0 D PORT1 Rin Sout PORT2 Sin ...
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MT9315 BCLK PORT1 ENA1 Rin Sout PORT2 ENA2 Sin Rout outputs = High impedance inputs = don’t care Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2 can ...
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Advance Information COMMAND/ADDRESS DATA 2 R Receive DATA 1 High Impedance Transmit SCLK CS This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT9315. The MT9315: latches ...
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MT9315 Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Input Voltage 3 Output Voltage Swing 4 Continuous Current on any digital pin 5 Storage Temperature 6 Package Power Dissipation * Exceeding these values may cause permanent damage. Functional operation under ...
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Advance Information DC Electrical Characteristics* Characteristics 11 Input capacitance 12 PWRDN Positive Threshold Voltage Hysteresis Negative Threshold Voltage ‡ Typical figures are and are for design aid only: not guaranteed and not subject to production testing. *DC ...
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MT9315 AC Electrical Characteristics Characteristics 1 Input Data Setup 2 Input Data Hold 3 Output Data Delay 4 Serial Clock Period 5 SCLK Pulse Width High 6 SCLK Pulse Width Low 7 CS Setup-Intel 8 CS Setup-Motorola 9 CS Hold ...
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Advance Information Bit 0 (1) Sout/Rout (2) BCLK SSS V (2) ENA1/ENA2 H or (2) V ENB1/ENB2 L Bit (3) Rin/Sin V L Notes: 1. CMOS output 2. TTL input ...
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MT9315 (1, 2) DATA1 V H (2) SCLK CSSI Notes: 1. CMOS output 2. TTL input compatible 3. CMOS input (see Table 8 for symbol definitions (2) DATA2 ...
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Advance Information Register Summary Address: 00h R Power Up LIMIT MUTE_R Reset 00h MSB RESET When high, the power initialization routine is executed presetting all registers to default values. This bit automatically clears itself to’0’ when reset is ...
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MT9315 Address: Acoustic Echo Canceller Status Register 22h Read 7 6 Power Up - ACMUND Reset 00h MSB NBS When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not been ...
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Advance Information Address: 16h Read 7 6 Power Up RIPD RIPD 7 Reset 00h MSB RIPD 0 RIPD 1 These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see ...
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MT9315 Address: Receive (Rin) ERROR Peak Detect Register 19h Read 7 6 Power Up REPD REPD 15 Reset 00h MSB REPD8 REPD9 See above description REPD10 REPD11 REPD12 REPD13 REPD14 REPD15 Address: Receive (Rout) Peak Detect Register 3Ah Read 7 ...
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Advance Information Address: 36h Read 7 6 Power Up SIPD SIPD 7 Reset 00h MSB SIPD 0 SIPD 1 These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see ...
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MT9315 Address: Send ERROR Peak Detect Register 39h Read 7 6 Power Up SEPD SEPD 15 Reset 00h MSB SEPD8 SEPD9 SEPD10 SEPD11 See Above description SEPD12 SEPD13 SEPD14 SEPD15 Address: 1Ah Read 7 6 Power Up SOPD SOPD 7 ...
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Advance Information Address: Acoustic Echo Canceller Adaptation Speed Register 3Ch R Power Up A_AS A_AS 7 Reset 00h MSB A_AS 0 This register allows the user to program control the adaptation speed of the Acoustic Echo Canceller. This ...
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MT9315 Address: Line Echo Canceller Adaptation Speed Register 1Dh R Power Up L_AS L_AS 15 Reset 08h MSB L_AS 8 L_AS 9 L_AS 10 See Above description L_AS 11 L_AS 12 L_AS 13 L_AS 14 L_AS 15 Address: ...
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Advance Information Address: 26h R Power Reset 3Dh MSB - - RESERVED - L 0 This register allows the user to program the output Limiter threshold value in the Rout path L 1 ...
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Package Outlines Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 8-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.115 (2.92) ...
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Notes Not to scale 2) Dimensions in inches 3) (Dimensions in millimeters) Plastic Dual-In-Line Packages (PDIP Suffix 22-Pin DIM Plastic Min Max A 0.210 (5.33) A 0.125 (3.18) 0.195 ...
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Package Outlines xxxx xxxxxxxxxxxxxxx xxxx xxxx x xxxx xxxxxxxxxxxxxxxxx Dim D ...
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