mt93l00av2 Zarlink Semiconductor, mt93l00av2 Datasheet

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... Fsel PLL C4i Timing F0i Unit DS CS R/W A10-A0 DTA Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved. Multi-Channel Voice Echo Canceller MT93L00AB MT93L00AV • Protection against narrow band signal divergence • ...

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... DTA VDD2 VSS MT93L00A MT93L00AB (100 pin LQFP) = 3.3 V DD1 Figure 2 - 100 Pin LQFP 2 Zarlink Semiconductor Inc. Data Sheet IC0 IC0 IC0 VSS IC0 IC0 IC0 IC0 VDD2 C4ib Foib Rin Sin Rout Sout ODE VSS ...

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... DD1 DD1 SS DD1 SS DD1 SS DTA IRQ DD1 DD1 DD1 Figure 3 - 208 Ball LBGA 3 Zarlink Semiconductor Inc. Data Sheet ICO ODE ...

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... CS to enable the read and write operations. CS Chip Select (Input). This active low input is used by a microprocessor to activate the microprocessor port. R/W Read/Write (Input). This input controls the direction of the data bus lines (D7-D0) during a microprocessor access. 4 Zarlink Semiconductor Inc. Data Sheet Description SS This output goes low for ...

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... Fsel Frequency select (Input). This input selects the Master Clock frequency operation. When Fsel pin is low, nominal 19.2 MHz Master Clock input must be applied. When Fsel pin is high, nominal 9.6 MHz Master Clock input must be applied. 5 Zarlink Semiconductor Inc. Data Sheet Description ...

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... MT93L00 into a low-power stand-by mode. When the RESET pin is returned to logic high and a clock is applied to the MCLK pin, the device will automatically execute initialization routines, which preset all the Control and Status Registers to their default power-up values. 6 Zarlink Semiconductor Inc. Data Sheet Description SS. DD2. ...

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... Offset + Processor Null - Microprocessor Interface Double-Talk Detector Narrow-Band Detector Linear Attenuator Echo Canceller (N), where 0 ≤ N ≤ Zarlink Semiconductor Inc. Data Sheet Linear/ Sout µ/A-Law (channel N) MuteS Path Change ST-BUS Detector PORT1 Disable Tone MuteR Detector Offset µ/A-Law/ ...

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... MT93L00A Lsin > Lrin + 20log (DTDT) 10 where DTDT is the Double-Talk Detection Threshold. DTDT = hex(DTDT * 32768) (hex) (dec) where 0 < DTDT < 1 (dec) 8 Zarlink Semiconductor Inc. Data Sheet ...

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... If the disable tone is present for a minimum of one second with at least one phase reversal, the Tone Detector will trigger. MT93L00A TSUP = Lrin + 20log (NLPTHR) 10 NLPTHR = hex(NLPTHR * 32768) (hex) (dec) where 0 < NLPTHR < 1 (dec) (hex) 9 Zarlink Semiconductor Inc. Data Sheet will reduce the noise level, values greater ...

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... The NBSD can be disabled by setting the NBDis bit to “1” in Control Register 2. MT93L00A Tone Detector ECA Status reg TD bit Tone Detector Echo Canceller A Tone Detector ECB Status reg TD Tone Detector Echo Canceller B Figure 5 - Disable Tone Detection 10 Zarlink Semiconductor Inc. Data Sheet bit ...

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... For a given group, only Echo Canceller A, Control Register A1, has the ExtDl bit. Control Register B1, bit-0 must always be set to zero. Table 2 shows the 16 groups of 2 cancellers that can each be configured into 128 ms echo tail capacity. MT93L00A 11 Zarlink Semiconductor Inc. Data Sheet ...

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... A Rout Rin PORT1 PORT2 b) Extended Delay Configuration (128 ms) Sin echo path Rout PORT2 c) Back-to-Back Configuration (64 ms) Figure 6 - Device Configuration 12 Zarlink Semiconductor Inc. Data Sheet CCITT (G.711) µ -Law A-Law FFh D5h channel Adaptive Filter (128 ms) channel A PORT1 Optional -12dB pad E ...

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... Figure 11). In GCI format, every second rising edge of the C4i clock marks the bit boundary, and data is clocked in on the second falling edge of C4i, half the way into the bit cell (see Figure 12). MT93L00A 125 µsec Channel 1 Channel 30 13 Zarlink Semiconductor Inc. Data Sheet Channel 31 ...

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... Noise Scaling 2Ah Injection Rate 2Bh Rin Peak Detect Reg 2Ch Sin Peak Detect Reg 2Eh Error Peak Detect Reg 30h Reserved 32h DTDT Reg 34h Reserved 36h NLPTHR 38h Step Size, MU 3Ah Reserved 3Ch Reserved 3Eh 14 Zarlink Semiconductor Inc. Data Sheet ...

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... MT93L00A Channel Group Table 2 - Group and Channel Allocation 15 Zarlink Semiconductor Inc. Data Sheet Channel 16, 17 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 ...

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... Channel Ctrl/Stat Registers Channel 30 Ctrl/Stat Registers 03C0h --> 03E0h --> Channel 31 Ctrl/Stat Registers 0400h --> 040Fh Main Control Registers <15:0> 0410h Interrupt FIFO Register Test Register 0411h Figure 9 - Memory Mapping 16 Zarlink Semiconductor Inc. Data Sheet 001Fh 003Fh 005Fh 007Fh 03DFh 03FFh to Base Address+ ...

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... Delay 100 s Reset High MCLK Active µ Delay 500 s Hardware Software Reg. Reset Reset Low PWUP to “1” Delay 1000 ns Delay 250 Reset High PWUP to “0” µ Delay 500 s ECAN Ready Nb_of_groups + 3. Zarlink Semiconductor Inc. Data Sheet µ s ...

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... TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to V when it is not driven from an external source. DD1 MT93L00A 18 Zarlink Semiconductor Inc. Data Sheet ...

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... The Bypass register is a single stage shift register that provides a one-bit path from TDI TDO. • Device Identification register The Device Identification register provides access to the following encoded information: device version number, part number and manufacturer's name. MT93L00A 19 Zarlink Semiconductor Inc. Data Sheet . SS ...

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... Note: Do not enable both Extended-Delay and BBM configurations at the same time. Control Register B1 bit reserved bit and should be written “0”. MT93L00A Read/Write Address Reset Value: AdpDis 0 ExtDl Read/Write Address Reset Value: AdpDis 1 0 Description 20 Zarlink Semiconductor Inc. Data Sheet + Base Address Base Address ...

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... When high, data on Sout is muted to quiet code. When low, Sout carries active code. 0 MuteR When high, data on Rout is muted to quiet code. When low, Rout carries active code. MT93L00A Read/Write Address: 01 Read/Write Address Reset Value: MuteS MuteR Description 21 Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address ...

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... The default value Step Size (SS)] where 7-0 =4, then the exponential decay start value is 512 - [NS 2-0 22 Zarlink Semiconductor Inc. Data Sheet Power Reset Value 00h Power Reset Value 00h Power Reset Value 04h Step Size (SS) ...

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... Reserved bit. Must always be set to zero for normal operation. MT93L00A Read Address: Read Address Reset Value: TDG NB Description Read/Write Address: 08 Read/Write Address PathDet res Reset Value: Description 23 Zarlink Semiconductor Inc. Data Sheet 02 + Base Address Base Address Base Address H + Base Address ...

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... Similarly, to scale dB, use a value of (dec) • 80h = 8Fh). Read/Write Address: 0Bh + Base Address Read/Write Address: 2Bh + Base Address Zarlink Semiconductor Inc. Data Sheet + Base Address H + Base Address Power Reset Value 74h Power Reset Value 0Ch ...

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... Read Address: 10h + Base Address Read Address: 30h + Base Address Zarlink Semiconductor Inc. Data Sheet Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A Power Reset Value N/A ...

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... Read/Write Address: 1Ah + Base Address Read/Write Address: 3Ah + Base Address (MU Zarlink Semiconductor Inc. Data Sheet Power Reset Value 48h (DTDT) 8 Power Reset Value 00h (DTDT) 0 Power Reset Value 0Bh (NLPTHR) Power Reset Value 60h (NLPTHR) ...

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... A/µ Law: When high, both Echo Cancellers A and B for a given group, accept A-Law companded PCM code. When low, both Echo Cancellers A and B for a given group, accept µ-Law companded PCM code. MT93L00A Read/Write Address: 400 Reset Value: LAW PWUP Description . 27 Zarlink Semiconductor Inc. Data Sheet ...

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... Two frames are necessary for the initialization routine to execute properly. Once the initialization routine is executed, the user can set the per channel Control Registers for their specific application. MT93L00A Read/Write Address: 400 LAW PWUP Reset Value: Description 28 Zarlink Semiconductor Inc. Data Sheet ...

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... Reset Value: LAW PWUP Description 29 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 401 H Read/Write Address: 402 H Read/Write Address: 403 H Read/Write Address: 404 H Read/Write Address: 405 ...

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... LAW PWUP Reset Value: Description 30 Zarlink Semiconductor Inc. Data Sheet Read/Write Address: 401 H Read/Write Address: 402 H Read/Write Address: 403 H Read/Write Address: 404 H Read/Write Address: 405 ...

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... Interrupt FIFO Register. When low, normal operation is selected. MT93L00A Read Address Reset Value: Description Read/Write Address: 411 1 0 Reset Value: res Tirq Description 31 Zarlink Semiconductor Inc. Data Sheet 410 (Read only ...

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... DD_IO I 65 DD_CORE P 150 C V 0.7V IH DD1 - 0.8V OH DD1 Zarlink Semiconductor Inc. Data Sheet Min. Max. -0.5 5.0 -0.5 2 0.5 V +0.5 SS DD1 V - 0.3 7 -55 150 ‡ Min. Typ. Max. Units -40 +85 3.0 3.3 3.6 1.7 1.8 1.9 V DD1 DD1 5.5 DD1 ...

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... Serial Streams for ST-BUS and GCI Backplanes ‡ Sym. Min. Typ. Max SIS 10 t SIH t 60 SOD t 30 ODE , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Conditions Units Notes Units Test Conditions ...

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... Bit 7, Channel 0 Bit 6, Channel Bit 1, Channel 0 Bit 2, Channel 0 t SIH Bit 1, Channel 0 Bit 2, Channel ODE ODE Valid Data V HiZ HiZ TT 34 Zarlink Semiconductor Inc. Data Sheet Bit 5, Channel ...

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... DDR t 3 DHR t 0 DSW t 0 DHW t AKD t 0 AKH t 20 IRD , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet ). unless otherwise stated. SS Units Notes MHz MHz Max. Units Test Conditions ...

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... READ D0-D7 WRITE DTA IRQ Figure 15 - Motorola Non-Multiplexed Bus Timing MT93L00A t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD 36 Zarlink Semiconductor Inc. Data Sheet CSH RWH ADH DHR DHW ...

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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...