alc888-vc2-gr Realtek Semiconductor Corporation, alc888-vc2-gr Datasheet - Page 28

• Manufacturer Part Number: alc888-vc2-gr
• Description: 7.1+2 Channel High Definition Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

Exit from ‘Link Reset’:
100µsec provides time for the codec PLL to stabilize)
last bit of frame SYNC, it means the codec requests an initialization sequence)
7.3.2.
A ‘Codec Reset’ is initiated via the codec RESET command verb. It results in the target codec being reset
to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
7.1+2 Channel High Definition Audio Codec
SYNC
BCLK
SDOs
RST#
SDIs
If BCLK is re-started for any reason (codec wake-up event, power management, etc.)
Software is responsible for de-asserting RST# after a minimum of 100µs BCLK running time (the
Minimum of 4 BCLK after RST# is de-asserted, the controller starts to signal normal frame SYNC
When the codec drives its SDI to request an initialization sequence (when the SDI is driven high at the
Codec Reset
1
2
SYNC is absent
Previous Frame
Normal Frame
3
Driven Low
Driven Low
Driven Low
4 BCLK
Figure 13. Link Reset Timing
4
4 BCLK
20
5
Pulled Low
Pulled Low
Pulled Low
Pulled Low
Link in Reset
6
>=100 usec
Track ID: JATR-1076-21
7
>= 4 BCLK
Wake Event
8
Initialization Sequence
Normal Frame
SYNC
Datasheet
ALC888
9
Rev. 1.4