SC92031L SILAN [Silan Microelectronics Joint-stock], SC92031L Datasheet - Page 26

• Manufacturer Part Number: SC92031L
• Description: 10/100 MBPS INTEGRATED PCI ETHERNET MEDIA ACCESS CONTROLLER AND PHYSICAL LAYER
• Manufacturer: SILAN [Silan Microelectronics Joint-stock]

CLS: Cache Line Size
LTR: Latency Timer Register
prior to count expiration, the content of the latency timer is ignored. Otherwise, after the count expires, the
SC92031 initiates transaction termination as soon as its GNTB is deasserted. Software is able to read or write,
and the default value is 00H.
HTR: Header Type Register
BIST: Built-in Self Test
IOAR: This register specifies the BASE I/O address which is required to build an address map during
registers. This register must be initialized prior to accessing any SC92031's register with memory access.
SVID: Subsystem Vendor ID. This field will be set to a value corresponding to PCI Subsystem Vendor ID in the
SMID: Subsystem ID. This field will be set to value corresponding to PCI Subsystem ID in the external EEPROM.
BMAR: This register specifies the base memory address for memory accesses to the SC92031 operational
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Read will return a zero, write are ignored.
Specifies, in units of PCI bus clocks, the value of the latency timer of the SC92031.
When the SC92031 asserts FRAMEB, it enables its latency timer to count. If the SC92031 deasserts FRAMEB
Read will return a zero, write are ignored.
Read will return a zero, write are ignored.
MEMAR: This register specifies the base memory address for memory accesses to the SC92031 operational
31-8
31-8
7-2
7-4
2-1
Bit
Bit
1
0
3
0
configuration. It also specifies the number of bytes required as well as an indication that it can be mapped
into I/O space.
external EEPROM. If there is no EEPROM, this field will default to a value of SILAN Semiconductor's PCI
Subsystem Vendor ID.
If there is no EEPROM, this field will default to a value of 2031h.
registers. This register must be initialized prior to accessing any SC92031 's register with memory access.
IOAR31-8
MEMSIZE
MEMLOC
MEM31-8
Symbol
Symbol
MEMPF
IOSIZE
MEMIN
IOIN
-
BASE I/O Address: This is set by software to the Base I/O address for the
operational register map.
Size Indication: Read back as a zero. This allows the PCI bridge to determine that
the SC92031 requires 256 bytes of I/O space.
Reserved
IO Space Indicator: Read only. Set to a one by the SC92031 to indicate that it is
capable of being mapped into IO space.
Base Memory Address: This is set by software to the base address for the
operational register map.
Memory Size: These bits return a zero, which indicates that the SC92031 requires
256 bytes of Memory Space.
Memory Prefetchable: Read only. Set to a zero by the SC92031.
Memory Location Select: Read only. Set to a zero by the SC92031. This indicates
that the base register is 32-bit wide and can be placed anywhere in the 32-bit
memory space.
Memory Space Indicator: Read only. Set to a zero by the SC92031 to indicate that
it is capable of being mapped into memory space.
Description
Description
REV:1.0
SC92031
Page 26 of 38
2004.08.03