mx25l512 Macronix International Co., mx25l512 Datasheet - Page 8

• Manufacturer Part Number: mx25l512
• Description: 512k-bit [x 1] Cmos Serial Flash
• Manufacturer: Macronix International Co.

Figure 2. SPI Modes Supported
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction sequence
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglected and
P/N: PM1214
Table 3. Memory Organization
Note:
CPOL indicates clock polarity of SPI master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which SPI mode is
supported.
(SPI mode 0)
(SPI mode 3)
next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
CS# rising edge.
difference of SPI mode 0 and mode 3 is shown as Figure 2.
is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following
instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.
not affect the current operation of Write Status Register, Program, Erase.
Sector
15
3
2
1
0
. .
.
CPOL
00F000h
003000h
002000h
001000h
000000h
0
1
Address Range
. .
.
CPHA
0
1
SI
SO
SCLK
SCLK
00FFFFh
003FFFh
002FFFh
001FFFh
000FFFh
. .
.
MSB
shift in
8
shift out
MX25L512
MSB
REV. 1.4, MAR. 24, 2008