mx25l6405 Macronix International Co., mx25l6405 Datasheet - Page 18

• Manufacturer Part Number: mx25l6405
• Description: Tm 64m-bit [x 1] Cmos Serial Eliteflash Memory
• Manufacturer: Macronix International Co.

P/N: PM1107
POWER-ON STATE
The device is at below states when power-up:
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during
power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and the flash device
has no response to any command.
For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device
is fully accessible for commands like write enable(WREN), page program (PP), sector erase(SE), chip erase(CE) and write
status register(WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The
write, erase, and program command should be sent after the below time delay:
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW
has not passed.
Please refer to the figure of "power-up timing".
Note:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
- tPUW after VCC reached VWI level
- tVSL after VCC reached VCC minimum level
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended.(generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any
command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.
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MX25L6405
REV.1.3, NOV. 06, 2006