mx25l12855e Macronix International Co., mx25l12855e Datasheet - Page 35

• Manufacturer Part Number: mx25l12855e
• Description: Secured Serial Flash
• Manufacturer: Macronix International Co.

P/N: PM1466
(31) Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specified block(or sector), using A23-A16 (or A23-A12) address bits to assign a 64K bytes block (4K
bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate
that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is
"0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send 3
address bytes to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high. (see
Figure 42)
(32) Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high. (see Figure 43)
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
(33) Clear SR Fail Flags (CLSR)
The CLSR instruction is for resetting the Program/Erase Fail Flag bit of Security Register. It should be executed be-
fore program/erase another block during programing/erasing flow without read array data.
The sequence of issuing CLSR instruction is: CS# goes low → send CLSR instruction code→ CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
(34) Output Driving Configure (ODC)
The ODC instruction is for changing the option value of output driving or sinking. The options of output current are
shown as follow table. In this table, bit [3:2] is for PMOS driving option and bit [1:0] is for NMOS sinking option.
The sequence of issuing ODC instruction is: CS# goes low→ send ODC instruction code→ set 8bit ODC data on SI (bit
[7:4] don't care)→ CS# goes high.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
Bit [3:2]
11
10
01
00
Output Drive current option
Output Driving
Current
2mA
1mA
6mA
4mA
For GPIO
For GPIO
Note
35
Bit [1:0]
10
01
00
11
Output Sink current option
MX25L12855E
Output Sinking
Current
-2mA
-1mA
-6mA
-4mA
REV. 0.05, MAR. 05, 2009
For GPIO
For GPIO
Note