mx25l1635dzni-10g Macronix International Co., mx25l1635dzni-10g Datasheet - Page 17

• Manufacturer Part Number: mx25l1635dzni-10g
• Description: Serial Flash Memory
• Manufacturer: Macronix International Co.

Status Register
P/N: PM1374
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register
data out on SO (see Figure 12)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction. The program/erase command will be ignored and
not affect value of WEL bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected
area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode
being set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruc-
tion to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector
Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruc-
tion can be executed).
QE bit. The Quad Enable (QE) bit, non-volatile bit, performs Quad when it is reset to "0" (factory default) to enable
WP# or is set to "1" to enable Quad SIO2 and SIO3.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, which is set to "0" (factory default). The
SRWD bit is operated together with Write Protection (WP#/SIO2) pin for providing hardware protection mode. The
hardware protection mode requires SRWD sets to 1 and WP#/SIO2 pin signal is low stage. In the hardware protec-
tion mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and
Block Protect bits (BP3, BP2, BP1, BP0) are read only.
Note 1: see the table 2 "Protected Area Size" in page 11.
SRWD (status
register write
register write
Non-volatile
1=status
protect)
disable
bit7
bit
0=not Quad
Non-volatile
1=Quad
Enable)
Enable
Enable
(Quad
bit6
QE
bit
Non-volatile
protected
(level of
(note 1)
block)
BP3
bit5
bit
Non-volatile
protected
(level of
(note 1)
block)
BP2
bit4
bit
17
Non-volatile
protected
(level of
(note 1)
block)
BP1
bit3
bit
Non-volatile
protected
(level of
(note 1)
block)
bit2
BP0
bit
MX25L1635D
(write enable
0=not write
volatile bit
1=write
enable
enable
latch)
WEL
bit1
REV. 1.7, MAR. 30, 2009
0=not in write
progress bit)
volatile bit
operation
operation
(write in
1=write
WIP
bit0