MK50H25N ST Microelectronics, Inc., MK50H25N Datasheet - Page 23

• Manufacturer Part Number: MK50H25N
• Description: High Speed Link Level Controller
• Manufacturer: ST Microelectronics, Inc.

09:08
07
06
05
04:03
02
FWM
BAE
BUSR
BSWPC
BURST
BSWPD
* Suggested setting
These bits define the FIFO watermarks. FIFO watermarks prevent the
MK50H25 from performing DMA transfers to/from the data buffers until
the FIFOs contain a minimum amount of data or space for data. For re-
ceive, data will only be transferred to the buffers after the FIFO has at
least N 16-bit words or end of frame has been reached. Conversely, for
transmit, data will only be transferred from the data buffers when the
transmit FIFO has room for at least N words of data. The Transmit
Threshold FIFO Watermark is also defined by these bits. If enabled by
setting XHOLD=1, the transmitter will be held-off from transmitting a
new frame until the transmit FIFO has at least N words of data, or the
entire frame has been placed in the FIFO. The N is defined as follows:
Bus Address Enable: If BAE is set, the A23-A20 pins are driven by the
MK50H25 constantly providing the ability to use A23-A20 for memory
bus selection. If clear, A23-A20 behave identically to A19- A16.
If this bit is set, pin 15 becomes input BUSREL. If this bit is clear
then pin 15 is either BM0 or BYTE depending on bit 00. For more in-
formation see the description for pin 15 in this document. BUSR is
READ/WRITE and cleared on bus Reset.
This bit determines the byte ordering of all "non-data" DMA transfers.
This transfers refers to any DMA transfers that access memory other
than the data buffers themselves. This includes the Initialization Block,
Descriptors, and Status Buffer. It has no effect on data DMA transfers.
BSWPC allows the MK50H25 to operate with memory organizations
that have bits 07:00 at even addresses and with bits 15:08 at odd ad-
dressses or vice versa. BSWPC is Read/Write and cleared by BUS
RESET.
With BSWPC = 1:
Address
With BSWPC = 0:
Address
This field determines the maximum number of data transfers performed
each time control of the host bus is obtained. BURST is READ/WRITE
and cleared on bus Reset.
This bit determines the byte ordering of all data DMA transfers.
Data transfers are those to or from a data buffer. BSWPD has no ef-
fect on non-data transfers. The effect of BSWPD on data transfers is
the same
above). For most applications, this bit should be set.
XX0
XX0
BURST <1:0>
FWM<1:0>
*
0
8
Suggested setting
11
10*
01
00
10*
00
01
. . .
. . .
as
15
7
that
of BSWPC on non-data transfers
8 bit mode
Not Allowed
9 words
17 words
25 words
unlimited
FWM N
16 bytes
2 bytes
Address
Address
XX1
XX1
0
8
. . .
. . .
15
7
16 bit mode
Not Allowed
19 words
11 words
3 words
XHOLD N
unlimited
1 words
8 words
MK50H25
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