hd66420 Renesas Electronics Corporation., hd66420 Datasheet - Page 44

• Manufacturer Part Number: hd66420
• Description: Ram-provided 160 Channel 4-level Grey Scale Driver For Dot Matrix Graphics Lcd
• Manufacturer: Renesas Electronics Corporation.

HD66420
Y Address Register (R3): The Y address register (figure 29) designates the Y address of the display RAM
to be accessed by the MPU. The set value must range from H’00 to H’40; setting a greater value is ignored.
The set address is automatically incremented each time the display RAM is accessed; it is not necessary to
update the address each time. Data bit 7 is unused; it should be set to 0 when written to.
Display Memory Access Register (R4): The display memory access register (figure 30) is used to access
the display RAM. If this register is write-accessed, data is directly written to the display RAM. If this
register is read-accessed, data is first latched to this register from the display RAM and sent out to the data
bus on the next read; therefore, a dummy read access is necessary after setting the display RAM address.
Display Start Raster Register (R5): The display start raster register (figure 31) designates the raster to be
displayed at the top of the LCD panel. Varying the set value scrolls the display vertically.
The set value must be one less than the actual top raster and less than the duty ratio. If the value is set
outside these ranges, data may not be displayed correctly. Data bits 7 is unused; they should be set to 0
when written to.
Blink Start Raster Register (R6): The blink start raster register (figure 32) designates the top raster in the
area to be blinked. The set value must be one less than the actual top raster and less than the duty ratio. If
the value is set outside these ranges, operations may not be correct. Data bits 7 is unused; they should be set
to 0 when written to.
Blink End Raster Register (R7): The blink end register (figure 33) designates the bottom raster in the area
to be blinked. The area to be blinked is designated by the blink registers, blink start raster register, and
blink end raster register. The set value must be one less than the actual bottom raster and less than the duty
ratio.
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Set value
Set value
Data bit
Set value
Data bit
Data bit
BIS1
7
7
7
Figure 28 X address Register (R2)
Figure 29 Y address Register (R3)
Figure 27 Control Register 2 (R1)
YA6 YA5 YA4 YA3 YA2 YA1
BIS0
6
6
6
WLS GRAY DTY1 DTY0
XA5
5
5
5
XA4
4
4
4
XA3
3
3
3
XA2
2
2
2
INC
XA1
1
1
1
YA0
XA0
BLK
0
0
0