hd66421 Renesas Electronics Corporation., hd66421 Datasheet - Page 37

• Manufacturer Part Number: hd66421
• Description: Ram-provided 160 Channel 4-level Grey Scale Driver For Dot Matrix Graphics Lcd
• Manufacturer: Renesas Electronics Corporation.

Control Register 2 (R1): Control register 2
(figure 34) controls general operations of the
HD66421. Each bit has its own function as
described below.
BIS1, BIS0 bits
WLS bit
GRAY bit
DTY1,DTY0 bits
INC bit
I NC = l: X address is incremented for each access
BLK bit
BIS1, 0 = (1, 1): 1/8 LCD drive levels bias ratio
BIS1, 0 = (1, 0): 1/9 LCD drive levels bias ratio
BIS1, 0 = (0, 1): 1/10 LCD drive levels bias ratio
BIS1, 0 = (0, 0): 1/11 LCD drive levels bias ratio
WLS = l: A word length is 6-bits
WLS = 0: A word length is 8-bits
GRAY = l : 4-levels of gray scale are fixed
GRAY = 0: 4-levels of gray scale are selected
DTY1, 0 = (1, 1): 1/8 display duty cycle; partial
DTY1, 0 = (1, 0): 1/64 display duty cycle
DTY1, 0 = (0, 1): 1/80 display duty cycle
DTY1, 0 = (0, 0): 1/100 display duty cycle
INC = 0: Y address is incremented for each access
BLK = 1: Blink function is used
BLK = 0: Blink function is not used
Preliminary
from 32-levels
Set value
Data bit
Set value
Data bit
Set value
Data bit
display mode
BIS1
7
7
7
Figure 34 Control Register 2 (R1)
Figure 35 X address Register (R2)
Figure 36 Y address Register (R3)
YA6
BIS0
6
6
6
YA5 YA4 YA3 YA2 YA1 YA0
WLS GRAY DTY1 DTY0
XA5
5
5
5
XA4
4
4
4
37
The blink counter is reset when the BLK bit is set
to 0. It starts counting and at the same time
initiates blinking when the BLK bit is set to l.
X Address Register (R2): The X address register
(figure 35) designates the X address of the
display RAM to be accessed by the MPU. The set
value must range from H'00 to H'27 in the case of
8-bit a word or range from H'00 to H'35 in the
case of 6-bit a word; setting a greater value is
ignored. The set address is automatically
incremented each time the display RAM is
accessed; it is not necessary to update the address
each time. Data bits 7 and 6 are unused; they
should be set to 0 when written to. When you use
monochrome display, the set value must range the
even number from H'00 to H'26 in the case of
8-bit a word or range from H'00 to H'34 in the
case of 6-bit a word.
Y Address Register (R3): The Y address register
(figure 36) designates the Y address of the
display RAM to be accessed by the MPU. The set
value must range from H'00 to H'40; setting a
greater value is ignored. The set address is
automatically incremented each time the display
RAM is accessed; it is not necessary to update the
address each time. Data bit 7 is unused; it should
be set to 0 when written to.
XA3
3
3
3
XA2
2
2
2
INC
XA1
1
1
1
BLK
XA0
0
0
0
Rev. 1.1E '99.02.10
HD66421