hd66731a01tb0l Renesas Electronics Corporation., hd66731a01tb0l Datasheet - Page 79

• Manufacturer Part Number: hd66731a01tb0l
• Description: Dot-matrix Liquid Crystal Display Controller/driver Supporting Japanese Kanji, Korean Font Display - Hitachi Semiconductor
• Manufacturer: Renesas Electronics Corporation.

HD66730/HD66731
Table 18
Reg. Index
No.
R8
R9
RF
Note: The execution time depends on the input or oscillation frequency.
BF = 1:
NF1/0:
LF0 to LF3: Position of display read raster-row
ID= 1:
RM1/0:
BST = 1:
EXT2 = 1:
EXT1 = 1:
DT1/0:
DCL = 1:
CHM = 1:
C = 1:
CM1/0:
ST = 1:
DC = 1:
DS = 1:
NC1/0:
NL1/0:
SN1/0:
SL0 to SL3: Designates scroll starting raster-row(0000: first raster-row, 1100: 13th raster-row)
PS1/0:
SE1 to SE4: Designates which line to scroll (SE = 1: enables the first line to be scrolled, etc.)
SQ0 to SQ5: Number of dots to scroll (0 to 48 dots)
RA0 to RA7: RAM address
RD0 to RD7: RAM data
78
= 0:
(Hex) Register R/W RS
8
9
F
RAM
address
(RAR)
RAM
data
(RDR)
Test
(TSR)
Instruction Registers (cont)
Internal processing being performed
Position of display read line
Address increment
Address decrement
RAM selection (00/01: DDRAM. (10: GGRAM, 11: SEGRAM)
Booster on
Common driver extension enable
Segment driver extension enable
Duty ratio (00: 1/14, 01: 1/27, 10: 1/40, 11: 1/53)
Executes display-clear instruction
Executes cursor-home instruction
Cursor on
Designates cursor mode (00: 12th raster-row, 01: blinking, 10: white/black inverse)
Standby mode
Character display on
Segment display on
Sets the number of display characters (6 to 40 characters)
Sets the number of display lines (00: 1 line, 01: 2 lines, 11: 4 lines)
Designates the line to start displaying (00: first line, 01: second line, 10: third line, 11: fourth
line)
Designates partial scroll (00: all columns scroll. 01: the leftmost column fixed, 10: the two
leftmost columns fixed, 11: the three leftmost columns fixed)
0
0/1
0
1
1
1
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 Resets the address
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 Writes or reads data to
0
0
0
Code
0
0
0
0
0
address counter for
DDRAM/CGRAM/
SEGRAM. RAM is
selected by RM1/0.
and from
DDRAM/CGRAM/
SEGRAM. RAM is
selected by RM1/0.
This is a test register.
Set 00 in this register.
Execution
Clock
Cycle
12
12
12