alc658 Realtek Semiconductor Corporation, alc658 Datasheet - Page 26

• Manufacturer Part Number: alc658
• Description: Six-channel Ac?97 2.3 Audio Codec
• Manufacturer: Realtek Semiconductor Corporation

6.1.25. MX3A S/PDIF Output Channel Status and Control
Default: 2000H
To ensure the control and status information was sent (starting at bit31) at the beginning of S/PDIF transmission, MX3A.[14:0]
should only be written to when the S/PDIF transmitter is disabled (MX2A.2=0).
If validity control is set (MX3A.15=1), the data bits (bit8 ~ bit27) should be forced to 0 to get better compatibility with
Minidiscs.
Six-Channel AC’97 2.3 Audio Codec
13:12
10:4
Bit
15
14
11
3
2
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
PRO=0
CC0
Function
Fs0
Validity Control (control V bit in Sub-Frame)
0: The V bit (valid flag) in the sub-frame depends on whether or not the S/PDIF FIFO has under-run
1: The V bit in the sub-frame is always sent as 1 to indicate the data is invalid.
DRS (Double Rate S/PDIF)
0: 32K, 44.1K, 48K S/PDIF-Out
1: 96K S/PDIF-Out
This bit only can be set when SPSR is 10b.
SPSR[1:0] (S/PDIF Out Sample Rate)
00: sample rate is 44.1KHz , Fs[0:3]=0000
01: Reserved
10: Sample rate is 48.0KHz when DRS=0, Fs[0:3]=0100 (default)
11: Sample rate set to 32.0KHz , Fs[0:3]=1100
LEVEL (Generation Level)
CC [6:0] (Category Code)
PRE (Pre-emphasis)
0: None
COPY (Copyright)
0: Asserted
/AUDIO (Non-Audio Data type)
0: PCM data
PRO (Professional or Consumer format)
0: Consumer format
The ALC658 only supports consumer channel status format. This bit is always 0
16
24
0
8
0
Sample rate is 96.0KHz when DRS=1, Fs[0:3]=0101
Table 31. MX3A S/PDIF Output Channel Status and Control
Table 32. Consumer Channel Status Block (bit0~bit31)
/AUDIO
CC1
Fs1
17
25
1
9
0
1: Filter pre-emphasis is 50/15 µsec
1: Not asserted
1: AC3 or other digital non-audio data
COPY
CC2
Fs2
10
18
26
2
0
1: Professional format
PRE
CC3
Fs3
19
27
11
3
0
22
CC4
12
20
28
4
0
0
0
CC5
13
21
29
5
0
0
0
CC6
14
22
30
6
0
0
0
LEVEL
15
23
31
7
0
0
0
Datasheet
ALC658
Rev. 1.3