sp5668 ETC-unknow, sp5668 Datasheet
sp5668
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sp5668 Summary of contents
Page 1
... The SP5668 is a single chip frequency synthesiser designed for tuning systems up to 2.7GHz. The RF preamplifer contains a divide by two prescaler which can be disabled for applications up to 2GHz so enabling a step size equal to the comparison frequency up to 2GHz and twice the comparison frequency up to 2.7GHz. ...
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... PHASE COMP BIT 16/17 COUNT 4 BIT CHARGE COUNT PUMP 1 BIT LATCH 18 BIT LATCH DISABLE 3 BIT DATA LATCH AND PORT INTERFACE INTERFACE Figure 2 - SP5668 block diagram Value Min Typ Max 100 300 300 300 0.7 10 -10 400 500 ...
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... MHz dBc/Hz 240 131071 480 262142 unused CC SP5668 Conditions See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Fig. 3 See Table 3, V =2V pin1 pin1 V = 0.7V PIN16 coupled sinewave AC coupled sinewave Applies to 4MHz crystal only. ...
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... The block diagram is shown in Fig.2. The SP5668 is controlled by a standard 3–wire bus com- prising data, clock and enable inputs. The programming word contains 27 bits are used for port selection, 2 the programmable divider ratio select the reference division ratio (Table1) ...
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... Phase Noise The SP5668 has been designed to offer good phase noise performance even when operated with a standard low profile 4MHz crystal and a high comparison frequency, e.g. 2MHz. The typical phase noise performance measured in the standard application is contained in Table 4. It has been demonstrated that even higher levels of performance will be achieved in a tuner application ...
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... SP5668 Preliminary Information comp (4MHz XTAL) 2GHz 1MHz 2GHz 2MHz +j0.2 0 –j0 NORMALISED CURRENT IN mA MIN TYP 0.23 0.30 0.68 0.90 Table 3 - Charge pump RF Division VCO PHASE RATIO NOISE @1kHZ OFFSET (dBc/Hz) 2000 1000 Table 4 - Typical phase noise +j1 +j0.5 +j2 0.2 0 ...
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... BCW31 Figure 7 - Typical application, SP5668 SP5668 OPERATING WINDOW 300 1000 2000 2700 FREQUENCY (MHz) Figure 5b - Typical input sensitivity (Prescaler enabled, PE=1) 38.9MHz VCO +5V +12V 16k 47k 2n2 TUNER OSCILLATOR OUTPUT 10n 3000 ...
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... SP5668 has been written. This covers aspects such as loop filter design and decoupling. This application note is also featured in the Media IC Handbook. A generic test/demo board has been produced which can be used for the SP5668. A circuit diagram is shown in Fig. 8. EXTERNAL REFERENCE C7 10nF ...
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... Loop Bandwidth The majority of applications for which the SP5668 is intended require a loop filter bandwidth of between 2kHz and 10kHz. Typically the VCO phase noise will be specified at both 1kHz and10kHz offset common practice to arrange the loop filter bandwidth such that the 1kHz figure lies within the loop bandwidth ...
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... SP5668 Preliminary Information V REF 500 500 RF INPUTS RF inputs V CC 25K Disable, Enable, Data and Clock inputs V CC XTAL CAP Reference oscillator BIAS Output Ports and Lock Output Figure 9 - Input/Output interface circuits CHARGE PUMP 200 DRIVE OUTPUT OS (Output disable) Loop amplifier ...
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For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors ...